Method of forming a multilayer structure

ABSTRACT

Method of forming a multilayer structure by electroetching or electroplating on a substrate. A seed layer is arranged on the substrate and a master electrode is applied thereto. The master electrode has a pattern layer forming multiple electrochemical cells with the substrate. A voltage is applied for etching the seed layer or applying a plating material to the seed layer. A dielectric material ( 9 ) is arranged between the structures ( 8 ) thus formed. The dielectric layer is planarized for uncovering the structure below and another structure layer is formed on top of the first. Alternatively, the dielectric layer is applied with a thickness two layers and the structure below is accessed by selective etching of the dielectric layer for selectively uncovering the top surface of the structure below. Multiple structure layer may also be formed in one step.

AREA OF INVENTION

The present invention relates to an etching and/or plating method forsimplifying production of applications involving micro and nanostructures in multiple layers. The method is particularly useful forfabrication of PWB (printed wiring boards), PCB (printed circuitboards), MEMS (micro electro mechanical systems), IC (integratedcircuit) interconnects, above IC interconnects, sensors, flat paneldisplays, magnetic and optical storage devices, etc. Different types ofstructures in conductive polymers, structures in semiconductors,structures in metals, and others are possible to produce using thismethod. Even 3D-structures in silicon, by using formation of poroussilicon, are possible to produce.

BACKGROUND ART

WO 02/103085 relates to an electrochemical pattern replication method,ECPR, and a construction of a conductive electrode for production ofapplications involving micro and nano structures. An etching or platingpattern, which is defined by a conductive electrode, master electrode,is replicated on an electrically conductive material, a substrate. Themaster electrode is put in close contact with the substrate and theetching/plating pattern is directly transferred onto the substrate byusing a contact etching/plating process. The contact etching/platingprocess is preformed in local etching/plating cells that are formed inclosed or open cavities between the master electrode and the substrate.

Patent application US 2005/0202180 discloses electrochemical fabricationmethods for forming single and multilayer mesoscale and microscalestructures. In the method, diamond machining (e.g. fly cutting orturning) is used to planarize layers. Moreover, sacrificial andstructural materials are described, which are useful in electrochemicalfabrication and which can be diamond machined with minimal tool wear(e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn and Au andSn—Pb, where the first material or materials are the structuralmaterials and the second is the sacrificial material). Methods forreducing tool wear are also described when using diamond machining toplanarize structures being electrochemically fabricated usingdifficult-to-machine materials, e.g. by depositing difficult to machinematerials selectively and potentially with little excess platingthickness, and/or pre-machining depositions to within a small incrementof desired surface level (e.g. using lapping or a rough cuttingoperation) and then using diamond fly cutting to complete the processand/or forming structures or portions of structures from thin walledregions of hard-to-machine material as opposed to wide solid regions ofstructural material.

A master electrode, which may be used in the present invention, isdescribed in Swedish patent application No. 0502539-2 entitled:“Electrode and method of forming the electrode” The content of thispatent specification is incorporated herein by reference.

A problem of prior art multilayer methods is the fact that during theplanarization step, at least two materials are required to be removed atthe same time. The problem is larger if the two materials have differentproperties, such as if one of the material is hard, such as a metal, andthe other material is soft, such as a plastics material, glass materialor porous material, for example a dielectricum.

If the planarization takes place by a mechanical polishing action orchemical-mechanical polishing action, several problems may arise. Suchpolishing action is performed by a plate which moves relative to thematerial to be planarized, such as by rotation, translation or rolling.

During the initial stage of the planarization, material is removed onlyat the top or ridges of the material. During this stage, there is a riskthat the underlying structure may be damaged, especially if the abrasionspeed is high. This risk may be decreased by partly dissolving thematerial by chemical means.

During the intermediate stage of the planarization, no specific problemsarise, but the abrasion is relatively straight forward, as long as onlythe soft or hard material is encountered.

During a final stage of the planarization, both soft material and hardmaterial may be removed. This may result in that the soft material isremoved at a higher rate than the hard material, known as erosion ordishing, resulting in recessions in the soft material between the hardmaterial. The final result may be unsuitable for the followingprocessing.

Another problem with mechanical planarization, it that there is a riskthat the plate is not completely parallel with the structure layerformed. A small angular deviation may result in that part of thestructure is not uncovered as desired.

A further problem of prior art multilayer methods is the fact that thethickness of the structure layer may be difficult to control.

A still further problem of prior art multilayer methods is the fact thatthe prior art method requires many process steps, which makes theprocess cumbersome and expensive.

A yet further problem of prior art multilayer methods is the fact thatit cannot fill vias or holes in the structure in an even manner.

Yet another problem is that it may be difficult to achieve a plane finalresult if the structures are relatively uneven from the start.

Further problems may be gathered from that stated below.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for formingmultilayer structures, in which the risk of erosion or dishing has beenreduced or even eliminated.

A further object is to provide a method of forming multilayerstructures, in which the number of steps may be reduced.

A still further object is to provide a method of forming multilayerstructures, in which vias can be filled in a uniform manner.

In an aspect of the invention, there is provided a method of forming amultilayer structure by electroplating on a substrate, comprising: a)arranging an electrically conducting seed layer on at least a part ofthe substrate or a substrate layer; b) applying a master electrode onsaid seed layer, said master electrode having an electrically conductingelectrode layer, an anode material and an insulating pattern layer forforming at least one electrochemical cell comprising an electrolyte inthe area enclosed by said anode material, said insulating pattern layerand said seed layer; wherein said anode material is being in electricalcontact with said conducting electrode layer; c) applying a voltagebetween said conducting electrode layer and said seed layer so that saidseed layer forms a cathode for transferring at least some of said anodematerial in said at least one cell to said seed layer for forming platedstructures corresponding to the cavities of the insulating pattern layeron the master electrode; d) separating said master electrode from saidsubstrate; e) removing said seed layer in non-plated areas; f) arranginga material in the areas in between the plated structures for forming amaterial layer that at least partly covers said plated structures; g)planarization of the material layer, until at least part of thestructures is uncovered; h) repeating at least some of said steps forproviding a multilayer structure.

In another aspect, there is provided a method of forming a multilayerstructure by electrochemical etching of a substrate, comprising: a)arranging an electrically conducting seed layer on at least a part ofthe substrate or a substrate layer; b) applying a master electrode onsaid seed layer, said master electrode having an electrically conductingelectrode layer and an insulating pattern layer for forming at least oneelectrochemical cell comprising an electrolyte in the area enclosed bysaid conducting electrode layer, said insulating pattern layer and saidseed layer; c) applying a voltage between said conducting electrodelayer and said seed layer so that said seed layer forms an anode foretching the seed layer and that said conducting electrode layer forms acathode for depositing etched material in said at least one cell forforming etched structures corresponding to the insulating pattern layeron the master electrode; d) separating said master electrode from saidsubstrate; e) removing possible remaining seed layer in between theetched structures; f) arranging a material in the areas between theetched structures for forming a material layer that at least partlycovers said etched structures; g) planarization of the material layer,until at least part of the structures is uncovered; h) repeating atleast some of said steps for providing a multilayer structure.

In an embodiment, the method may further comprise: planarization of thematerial layer, until at least part of the structures is almostuncovered; removing further material by a removal method havingsubstantially uniform removal rate over the entire surface until atleast a part of the structures is uncovered. The method may furthercomprise: between the steps d) and e) applying a further masterelectrode for forming electrochemical cells with the structurespreviously formed; and applying a voltage for forming a further layer ofplated structures on top of the previously formed layer of structures.The step of planarization may be performed by at least one polishingand/or etching step. The step of polishing may comprise removing aportion of said material layer by an abrasive action. The at least onepolishing step may be performed by a method selected from the groupcomprising: mechanical-polishing, chemical-polishing,chemical-mechanical-polishing (CMP), contact planarization (CP),planarization with a doctor blade, and combinations thereof. Thepolishing step may be performed by CMP or CP. The at least one etchingstep may be performed by a method selected from the group comprising:dry-etching methods, ion-sputtering, reactive-ion-etching (RIE),plasma-assisted-etching, laser-ablation, ion-milling, and combinationsthereof.

In a further aspect, there is provided a method of forming a multilayerstructure by electroplating on a substrate, comprising: a) arranging anelectrically conducting seed layer on at least a part of the substrateor a substrate layer; b) applying a master electrode on said seed layer,said master electrode having an electrically conducting electrode layer,an anode material and an insulating pattern layer for forming at leastone electrochemical cell comprising an electrolyte in the area enclosedby said anode material, said insulating pattern layer and said seedlayer; wherein said anode material is being in electrical contact withsaid conducting electrode layer; c) applying a voltage between saidconducting electrode layer and said seed layer so that said seed layerforms a cathode for transferring at least some of said anode material insaid at least one cell to said seed layer for forming plated structurescorresponding to the cavities of the insulating pattern layer on themaster electrode; d) separating said master electrode from saidsubstrate; e) removing said seed layer in non-plated areas; f) arranginga material in the areas in between the plated structures for forming amaterial layer that covers said plated structures; i) providing recessesin said material layer for uncovering at least a part of the platedstructure there below; h) repeating at least some of said steps forproviding a multilayer structure.

In a still further aspect, there is provided a method of forming amultilayer structure by electrochemical etching of a substrate,comprising: a) arranging an electrically conducting seed layer on atleast a part of the substrate or a substrate layer; b) applying a masterelectrode on said seed layer, said master electrode having anelectrically conducting electrode layer and an insulating pattern layerfor forming at least one electrochemical cell comprising an electrolytein the area enclosed by said conducting electrode layer, said insulatingpattern layer and said seed layer; c) applying a voltage between saidconducting electrode layer and said seed layer so that said seed layerforms an anode for etching the seed layer and that said conductingelectrode layer forms a cathode for depositing etched material in saidat least one cell for forming etched structures corresponding to theinsulating pattern layer on the master electrode; d) separating saidmaster electrode from said substrate; e) removing possible remainingseed layer in between the etched structures; f) arranging a material inthe areas between the etched structures for forming a material layerthat covers said etched structures; i) providing recesses in saidmaterial layer for uncovering at least a part of the etched structurethere below; h) repeating at least some of said steps for providing amultilayer structure.

In an embodiment, the step of providing recesses in said material layermay be performed by a lithographic method selected from the groupcomprising: photolithography, laser lithography, E-beam lithography,nanoimprinting and combinations thereof. The lithographic method mayfurther comprise patterning an etch-mask and etching said material layerwith dry-etching methods, such as ion-sputtering, reactive-ion-etching,plasma-assisted-etching, laser-ablation, ion-milling or combinationsthereof. The etch-mask may comprise a material selected from the groupcomprising: a resist, such as a photoresist; a hard-mask, such as SiN,SiO₂, SiC, tetraethyl orthosilicate (TEOS), SiON, SiOC, SiCN:H,(non-porous) fluorine doped silicon glass (FSG), (non-porous) organicdoped silicon glass (OSG), a low-k dielectric barrier/etch stop filmsuch as BLok™, Pt, Ti, TiW, TiN, Al, Cr, Au, Ni, Cu, Ag, metals and bycombinations thereof. The etch-mask may be dry-etched using a resist,such as a photoresist, as a mask; whereas said resist may be patternedwith said lithographic method. The etch-mask may be formed by saidstructure layer in said step c). The step of arranging material in theareas between the plated or etched structures may be performed forforming a material layer having at least the thickness of two structurelayers.

In another embodiment, the material layer may be planarized beforeproviding recesses.

In a further embodiment, the method may further comprise applying abarrier/capping layer before step a). The method may further compriseapplying a barrier/capping coating before step f).

The seed layer may be made of a material selected from the groupcomprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys ofthese material, Si, conducting polymers such as polyaniline; soldermaterials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel andpermalloy; and combinations thereof. The seed layer may be applied by amethod selected from the group comprising: chemical-vapor-deposition(CVD), metallorganic-chemical-vapor-deposition (MOCVD),physical-vapor-deposition (PVD), atomic layer deposition (ALD),sputtering, electroless plating, electroplating, electro-grafting, andimmersion deposition.

The material layer may be a layer of a dielectric material and isapplied by a method selected from the group comprising: spin-coating,spray-coating, powder-coating, dip-coating, roller-coating, sputtering,PVD, CVD, Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD),electrodeposition, and combinations thereof. The dielectric material maycomprise at least one layer of a material selected from the groupcomprising: low-k dielectric materials, ultra low-k dielectrics,dielectric materials with k-value less than 4, dielectric materials withk-value less than 2.5; organic compounds, insulating in-organiccompounds, oxides, nitrides, polymer materials, polyimide, siloxanemodified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE),silicones, elastomeric polymers, E-beam resists, ZEP (Sumitomo),photoresists, thinfilm resists, thickfilm resists, polycyclic olefins,polynorborene, polyethene, polycarbonate, PMMA, BARC materials,Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers,fluoro elastomers, acrylate polymers, (natural) rubber, silicones,lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene,fluoromethylene cyanate ester, inorganic-organic hybrid polymers,(fluorinated and/or hydrogenated) amorphous carbon, organic dopedsilicon glass (OSG), fluorine doped silicon glass (FSG), PFTE/siliconcompound, tetraethyl orthosilicate (TEOS), SiN, SiO₂, SiON, SiOC,SiCN:H, SiOCH materials, SiCH materials, silicates, silica basedmaterials, silsesquioxane (SSQ) based material, (nanoporous)methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO₂, Al₂O₃,TiN and combinations thereof.

In a yet further aspect, there is provided a method of forming amultilayer structure by electrochemical plating on a substrate, whereinsaid substrate or said substrate layer comprises a via, the methodcomprising; a) arranging an electrically conducting seed layer on atleast a part of the substrate or a substrate layer and said via; b)applying a master electrode, in which said insulating pattern layer isprovided with cavities at least opposite to said vias, and wherein saidcavities have a width which is slightly smaller, equal or slightlylarger than the width of said via; and a predeposited anode material isarranged in said cavities; c) applying a voltage between said conductingelectrode layer and said seed layer for transferring at least some partsof said anode material for forming plated structures in said vias.

In an embodiment, the seed layer is made of a material selected from thegroup comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloysof these material, Si, conducting polymers such as polyaniline; soldermaterials, such as SnPb, SnAg, SnAgCu, SnCu; alloys, such as monel andpermalloy; and combinations thereof. The seed layer may be applied by amethod selected from the group comprising: chemical-vapor-deposition(CVD), metallorganic-chemical-vapor-deposition (MOCVD),physical-vapor-deposition (PVD), atomic layer deposition (ALD),sputtering, electroless plating, electroplating, electro-grafting, andimmersion deposition.

In a yet still further aspect, there is provided a method of forming astructure by electrochemical plating on a substrate provided with aconducting material structure, comprising: a) arranging an electricallyconducting seed layer on at least a part of the substrate; b) applying amaster electrode on said seed layer, said master electrode having anelectrically conducting electrode layer, an anode material and aninsulating pattern layer for forming at least one electrochemical cellcomprising an electrolyte in the area enclosed by said anode material,said insulating pattern layer and said seed layer, said cavity enclosingat least a part of said conducting material structure; wherein saidanode material is being in electrical contact with said conductingelectrode layer; c) applying a voltage between said conducting electrodelayer and said seed layer so that said seed layer forms a cathode fortransferring at least some of said anode material in said at least onecell to said seed layer for forming plated structures onto said seedlayer and said conducting material structures corresponding to thecavities of the insulating pattern layer on the master electrode; d)separating said master electrode from said substrate.

The method may further comprise: b1) applying a further master electrodeon said seed layer, said master electrode having an electricallyconducting electrode layer, an anode material and an insulating patternlayer for forming at least one electrochemical cell comprising anelectrolyte in the area enclosed by said anode material, said insulatingpattern layer and said seed layer, said cavity enclosing at least a partof said conducting material structure and plated structures; whereinsaid anode material is being in electrical contact with said conductingelectrode layer; c1) applying a voltage between said conductingelectrode layer and said seed layer so that said seed layer forms acathode for transferring at least some of said anode material in said atleast one cell to said seed layer for forming plated structures ontosaid seed layer and said conducting material structures and platedstructures corresponding to the cavities of the insulating pattern layeron the master electrode; d1) separating said master electrode from saidsubstrate. The method may further comprise: e) removing said seed layerin non-plated areas.

In an embodiment, the planarization step may comprise performing apolishing step until said material surface is substantially planar and asubsequent etching step of said material surface until at least part ofsaid structures is uncovered. A planarizing material may be applied intosaid material layer prior to performing said planarization step of saidmaterial layer. The planarizing material may be applied with a methodselected from the group comprising: spin-coating, spray-coating,powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD,PECVD, electrodeposition, and combinations thereof.

In another embodiment, an end-point detection method may be used so asto determine when said planarization step is completed. The end-pointdetection method may be selected from the group comprising: detectingwhen said structure material is being abraded or etched; determining theheight of said material layer; and analyzing the color of said materiallayer. The detection may be based on interferometry of spectral analysisof said abraded material or said height is being determined by lasermeasurements or said color of said material is analyzed by using asensor and a camera. The step of contact planarization may comprise:applying a plate above said material layer and applying a pressure onsaid plate for equalizing the material in said material layer, while ina flowable condition. The flowable condition may be obtained by heatingsaid material layer, whereupon the material is cooled afterplanarization. The step of applying the plate is performed before curingsaid material, whereupon the material is cured after planarization, suchas by applying infrared or ultraviolet radiation.

In a further embodiment, the seed layer is applied by a method selectedfrom the group comprising: chemical-vapor-deposition (CVD),metallorganic-chemical-vapor-deposition (MOCVD),physical-vapor-deposition (PVD), atomic layer deposition (ALD),sputtering, electroless plating, electroplating, electro-grafting,immersion deposition, and combinations thereof. The arranging of a seedlayer; and/or said arranging of a material; and/or said plating; and/orsaid etching; are performed by a method resulting in a controlledthickness.

In yet an embodiment, the method further comprises applying abarrier/capping layer before step a) and/or before step f). Thebarrier/capping material may comprise at least one layer of materialthat prevents corrosion, diffusion or electromigration of layers, whichare interfacing with said barrier/capping material. The barrier/cappingmaterial may be selected from the group comprising: Ti, TiN, TiW, Cr,Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os,Hf, Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof andcombinations thereof. The barrier/capping material may be applied by amethod selected from the group comprising electrodeposition, MOCVD, CVD,PVD, ALD, sputtering, electroless deposition, immersion deposition,electrografting and combinations thereof. The barrier/capping materialmay be applied with a mask-less selective deposition method, such aselectroless deposition, wherein deposition is obtained only in surfacesactive to said deposition process, such as on said structure layer andnot on said arranged material layer.

The said barrier/capping material may be used as a seed layer in saidstep a). The seed layer may be made of a material selected from thegroup comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, TiN, TiW, Ni,NiB, NiP, NiCo NiBW, NiM-P, Al, Pd, Pt, W, Ta, TaN, Rh, Wo, Co, CoReP,CoP, CoWP, CoWB, CoWBP alloys of these material, Si, conducting polymerssuch as polyaniline; solder materials, such as SnPb, SnAg, SnAgCu, SnCu;alloys, such as monel and permalloy; and alloys thereof and combinationsthereof. The seed layer may be cleaned and activated, wherein saidcleaning and activation comprise using organic solvents, such as acetoneor alcohols; and/or inorganic solvents, such as nitric acid, sulfuricacid, phosphoric acid, hydrochloric acid, acetic acid, hydrofluoricacid; strong oxidizing agents, such as peroxides, such ashydrogen-peroxide; persulfates, such as sodium-persulfate orammonium-persulfate; ferric-chloride; and/or oxygen plasma; argonplasma; hydrogen plasma; and/or by mechanically removing impurities.

In yet a further embodiment, the method may further comprise applying anadhesion layer before applying said seed layer and/or before applyingsaid barrier/capping material; wherein said adhesion layer increase theadhesion of said seed layer or barrier/capping layer to said arrangedmaterial layer or structures. The adhesion layer may comprise at leastone material selected from the group comprising: Cr, Ti, TiW, AP-3000(Dow Chemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources),AP-300 (Silicon Resources) and combinations thereof.

In a yet further embodiment, the forming of at least one electrochemicalcell comprises a method for aligning said insulating pattern layer to apatterned layer on said substrate. The aligning method may compriseusing alignment marks on the front side and/or backside of said masterelectrode, which marks are aligned to corresponding alignment marks onsaid substrate. The aligning method may be performed prior to forming atleast one electrochemical cell. The formed electrochemical cell maycomprise a solution of cations, such as copper or nickel ions, andanions, such as sulfate ions, for electrochemical etching and/orplating. The electrolyte may comprise suppressors, levelers and/oraccelerators, for instance PEG (poly-ethylene glycol) together withchloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSAand/or sodium-lauryl-sulphate.

In an embodiment, the structure layer may be a material selected fromthe group comprising: Au, Ag, Ni, Cu, Sn, Pb, SnAg, SnAgCu, AgCu andcombinations thereof. The structure layer may comprise Cu or Ni. Theanode material may be arranged onto said conducting electrode layer inthe cavities of said insulating pattern layer using a method selectedfrom the group comprising: electroplating, electroless plating,immersion plating, CVD, MOCVD, powder-coating, chemical grafting,electrografting and combinations thereof. The method for arranging saidanode material may comprise electroplating or electroless plating. Theforming of structures is stopped, by disconnecting said voltage, priorto dissolving all or substantially of the anode material. At least 5% ofthe anode material may be remaining when said forming of structures isstopped. The depth of said etched structures or the thickness of saidplated structures may be controlled by monitoring the time and currentpassing through said at least one electrochemical cell.

In a further embodiment, the separation step d) may be performed byholding said substrate in a fixed position and moving said masterelectrode in a direction perpendicular to the substrate surface; or byholding said master electrode in a fixed position and moving saidsubstrate in a direction perpendicular to the master electrode surface;or by performing the separation in a less parallel manner so as to easethe separation; or by a combination thereof. The step e) removing saidseed layer may be performed by wet-etching, dry-etching, electrochemicaletching or by combinations thereof.

In an embodiment, the method further comprises applying a protectivecoating which is covering all or substantially all of said seed layer,barrier/capping layer and/or structure layer; treating said protectivecoating with an anisotropic etch, thereby uncovering the top of saidseed layer, barrier/capping layer and/or structure layer between thestructures while leaving a protective layer on the side walls of saidstructures; removing said seed layer and/or barrier layer between saidstructures.

The material layer may be at least one layer of a dielectric materialand may be applied by a method selected from the group comprising:spin-coating, spray-coating, powder-coating, dip-coating,roller-coating, sputtering, PVD, CVD,Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition,and combinations thereof. The material layer may be at least one layerof a metal and may be applied by a method selected from the groupcomprising: electrodeposition, MOCVD, CVD, PVD, ALD, sputtering,electroless deposition, immersion deposition, electrografting andcombinations thereof. The dielectric material may comprise at least onelayer of a material selected from the group comprising: low-k dielectricmaterials, ultra low-k dielectrics, dielectric materials with k-valueless than 4, dielectric materials with k-value less than 2.5; organiccompounds, insulating in-organic compounds, oxides, nitrides, polymermaterials, polyimide, siloxane modified polyimide, BCB, SU-8,polytetrafluoroethylene (PTFE), silicones, elastomeric polymers, E-beamresists, ZEP (Sumitomo), photoresists, thinfilm resists, thickfilmresists, polycyclic olefins, polynorborene, polyethene, polycarbonate,PMMA, BARC materials, Lift-Off-Layer (LOL) materials, PDMS,polyurethane, epoxy polymers, fluoro elastomers, acrylate polymers,(natural) rubber, silicones, lacquers, nitrile rubber, EPDM, neoprene,PFTE, parylene, fluoromethylene cyanate ester, inorganic-organic hybridpolymers, (fluorinated and/or hydrogenated) amorphous carbon, organicdoped silicon glass (OSG), fluorine doped silicon glass (FSG),PFTE/silicon compound, tetraethyl orthosilicate (TEOS), SiN, SiO₂, SiON,SiOC, SiCN:H, SiOCH materials, SiCH materials, silicates, silica basedmaterials, silsesquioxane (SSQ) based material, (nanoporous)methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO₂, Al₂O₃,TiN and combinations thereof.

In a further embodiment, the method further comprises: arranging anetch-stop layer on top of the structures before the step f) of arrangingthe material. The etch-stop layer may comprise at least one layer of amaterial selected from the group comprising: SiC, SiN, films, low-kdielectric barrier/etch stop films, such as BLOk™; Ti, TiN, TiW, Cr, Ni,NiB, NiP, NiCo NiBW, NiM-P, Pd, Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf,Rh, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, alloys thereof andcombinations thereof. The material layer may be a porous low-kdielectric material and a pore sealing operation may be performed priorto applying further layers of material onto it.

In a further embodiment, the material layer may be a sacrificialpolymer, wherein said sacrificial polymer is being decomposed intogaseous phase when treated with heat or radiation. The sacrificialpolymer may be a copolymer of butylnorbornene and triethoxysilylnorbornene, such as Unity Sacrificial Polymer™ (Promerus).

In a further embodiment, the method may further comprise: forming astructure layer before step h); wherein forming a structure layer maycomprise lithography methods; deposition methods such aselectrodeposition, electroless deposition; wet-etching or dry-etchingmethods.

BRIEF DESCRIPTION OF DRAWINGS

Further objects, features and advantages of the invention will appearfrom the following detailed description of several embodiments withreference to the drawings, in which:

FIGS. 1( a) to 1(h) are schematic cross-sectional views disclosingseveral method steps of a first embodiment comprising etching.

FIGS. 2( a) to 2(p) are schematic cross-sectional views disclosingseveral method steps of a second embodiment comprising plating.

FIGS. 3( a) to 3(l) are schematic cross-sectional views disclosingseveral method steps of a third embodiment comprising etching and inwhich a dielectric material layer is applied with a thickness of twolayers.

FIGS. 4( a) to 4(m) are schematic cross-sectional views disclosingseveral method steps of a fourth embodiment comprising plating and inwhich a dielectric material layer is applied with a thickness of twolayers.

FIGS. 5( a) to 5(l) are schematic cross-sectional views disclosingseveral method steps of a fifth embodiment comprising plating and inwhich a dielectric material layer is applied with a thickness of twolayers followed by plating also with a thickness of two layers.

FIGS. 6( a) to 6(n) are schematic cross-sectional views disclosingseveral method steps of a sixth embodiment comprising plating and inwhich a dielectric material layer is planarized in two steps.

FIGS. 7( a) to 7(b) are schematic cross-sectional views disclosingmethod steps of a seventh embodiment comprising plating and in which avia is filled with plating material.

FIGS. 8( a) to (b) are schematic cross-sectional views disclosing methodsteps of an eight embodiment comprising plating and in which a via isfilled with plating material.

FIGS. 9( a) to (c) are schematic cross-sectional views disclosing methodsteps of a ninth embodiment comprising plating and in which a via isfilled with plating material.

FIGS. 10( a) to (c) are schematic cross-sectional views disclosingmethod steps of a tenth embodiment comprising plating and in which a viais filled with plating material.

FIGS. 11( a) to (c) are schematic cross-sectional views disclosingmethod steps of an eleventh embodiment comprising plating and in which avia is filled with plating material.

FIGS. 12( a) to (b) are schematic cross-sectional views disclosingmethod steps of a twelfth embodiment comprising plating and in which avia is filled with plating material.

FIGS. 13( a) to (c) are schematic cross-sectional views disclosingmethod steps of a thirteenth embodiment comprising plating and in whicha via is filled with plating material.

FIGS. 14( a) to (c) are schematic cross-sectional views disclosingmethod steps of a fourteenth embodiment comprising plating and in whicha via is filled with plating material.

FIGS. 15( a) to (b) are schematic cross-sectional views disclosingmethod steps of a fifteenth embodiment comprising plating and in which aconducting or non-conducting material is enclosed by a plating material.

FIGS. 16( a) to (d) are schematic cross-sectional views disclosingmethod steps of a sixteenth embodiment comprising plating and in which aconducting or non-conducting material is enclosed by a plating material.

FIGS. 17( a) to (h) are schematic cross-sectional views disclosingdifferent embodiments of a master electrode.

FIG. 18 is a schematic flow scheme of the method steps of a conventionallithographic and electroplating process.

FIG. 19 is a schematic flow scheme of the method steps of the inventivemethod.

FIG. 20 (a) to (b) are schematic cross-sectional views disclosing anelectrode having no predeposited material and en electrode havingpredeposited material, respectively.

DETAILED DESCRIPTION OF EMBODIMENTS

Below, embodiments including the best mode of the invention will bedescribed in great detail in order to enable a skilled person to carryout the invention.

All embodiments described below comprise one or several of a number ofmethod steps. Each of these steps will be described separately in detailbelow.

Generally, the method steps comprises one or several of the followingsix steps, namely:

a) arranging a seed layer on top of a substrate, or on top of a previouslayer;

b) putting a master electrode in contact with the substrate, such as theseed layer, to form multiple electrochemical cells;

c) forming structures in said seed layer by etching or formingstructures on said seed layer by plating;

d) removal of the master electrode;

e) possible removal of seed layer;

f) applying a dielectric material layer; and

possible planarizing and/or patterning of the dielectric material layer.

In a first step (a) the substrate is prepared by applying a seed layeron top of said supplied substrate. In some embodiments, abarrier/capping and/or adhesion layer is deposited on the substrateprior to applying the seed layer or arranged below the seed layer beforebeing applied on the substrate.

Said seed layer comprises at least one, normally relatively thin layerof conducing material onto which material, such as predeposited anodematerial in the master electrode, can be plated with the ECPR platingprocess. Alternatively, the seed layer comprises at least one, normallyrelatively thick layer of conducing material in which structures can beetched with the ECPR etching process.

Since the seed layer forms one of the electrodes of the electrochemicalcell, the seed layer must be applied at least where a cell is to beformed. Moreover, the seed layer must be able to be electricallycontacted from the outside of the substrate or through conducting partsof the substrate, which is connected with the seed layer, or via themaster electrode. Thus, the seed layer can be arranged covering only therequired surfaces. However, the seed layer can be applied over theentire surface of the substrate to be acted upon.

The seed layer can be comprised of one or several layers of any of thematerials Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, Ni, Al, alloys ofthese material, Si, other metals such as used for barrier/capping and/oradhesion layers mentioned below, conducting polymers such aspolyaniline, solder materials such as SnPb, SnAg, SnAgCu, SnCu, alloyssuch as monel or permalloy and/or combinations thereof.

The seed layer can be applied by chemical-vapor-deposition (CVD),metallorganic-chemical-vapor-deposition (MOCVD),physical-vapor-deposition (PVD), atomic layer deposition (ALD),sputtering, electroless plating, electroplating, electro-grafting,immersion deposition and/or by other processes including applying layersof conducting material. When the seed layer is to be arranged onconducting as well as non-conducting areas of the substrate at the sametime, vapor-deposition or sputtering techniques can be used. If the seedlayer is to be relatively thick, electroplating may be used to form alayer having a relatively uniform upper surface independent on anyrecesses in the substrate surface. More in detail, a uniform uppersurface can be achieved by using additives such as suppressors,levelers, accelerators and/or wetting agents, for instance PEG(poly-ethylene glycol) and chloride ions, SPS(bis-(3-sulfopropyl)-disulfide) and/or sodium-lauryl-sulphate used forcopper plating, that increase the electrodeposition speed in the recessand/or by using pulse plating, for instance pulse-reverse-plating whichalso evens out height differences in the deposited layer. Using anyapplication method, a uniform upper surface can be achieved independenton any recess in the substrate, specifically if the thickness of theseed layer is significantly larger than the depth of the recesses.

The seed layer of the substrate can be cleaned and activated beforeusage in the ECPR process. The cleaning method can include the use oforganic solvents e.g. acetone or alcohols; and/or inorganic solventse.g. nitric acid, sulfuric acid, phosphoric acid, hydrochloric acid,acetic acid, hydrofluoric acid, strong oxidizing agents, e.g. peroxides,persulfates, ferric-chloride, and/or de-ionized water. Cleaning can alsobe performed by applying oxygen plasma, argon plasma and/or hydrogenplasma or by mechanically removing impurities. Activation of the seedlayer surface can be performed with solutions removing oxides, e.g.sulfuric acid, nitric acid, hydrochloric acid, hydrofluoric acid,phosphoric acid and etchants, e.g. sodium-persulfate,ammonium-persulfate, hydrogen-peroxide, ferric-chloride and/or othersolutions comprising oxidizing agents.

Said barrier/capping layer can be comprised of at least one layer of atleast one material or a combination of materials that: prevents saidconducting material from corrosion; prevents said conducting materialfrom diffusing into interfacing materials; prevents electro-migrationand/or prevents other phenomena having negative effect on the electricalproperties of the manufactured substrate. The barrier/capping layer canbe comprised of Ti, TiN, TiW, Cr, Ni, NiB, NiP, NiCo NiBW, NiM-P, Pd,Pt, Au, Ag, W, Ru, Ta, TaN, Re, Os, Hf, Rh, Wo, Co, CoReP, CoP, CoWP,CoWB, CoWBP, alloys thereof and/or combinations thereof.

Said adhesion layer can be comprised of material or a combination ofmaterials that increase the adhesion of the conducting seed layermaterial or barrier/capping material to the dielectric layer. Theadhesion layer can be comprised of Cr, Ti, TiW, AP-3000 (Dow Chemicals),AP-100 (Silicon Resources), AP-200 (Silicon Resources) and/or AP-300(Silicon Resources). The adhesion layer can in some embodiments alsofunction as a catalytic layer facilitating and/or improving thedeposition of the seed layer. The barrier/capping and/or adhesion layerscan be applied by using deposition methods such as electrodeposition,MOCVD, CVD, PVD, ALD, sputtering, electroless deposition, immersiondeposition, electrografting and/or other deposition methods suitable forthe barrier/capping and/or adhesion materials.

The barrier/capping layer and/or adhesion layer can, in someembodiments, be applied with a mask-less selective deposition processsuch as electroless deposition and/or chemical grafting, wherebydeposition is obtained only on surfaces active in relation to saiddeposition processes, for instance on a structure layer and not on adielectric layer.

In some embodiments the seed layer also functions as a barrier/cappinglayer, for instance when applying a Ru layer. In other embodiments, abarrier/capping layer can be used as a seed layer. In some embodiments,said barrier/capping layer needs to be activated in order to function asa seed layer. Such surface activation can be Sn, or Pd activation, forinstance by treating the surface with a PdCl₂ and/or SnCl₂ solution. Asolution for Pd activation can be PdCl₂ in diluted HCl. In someembodiments, HF is added to the activation solution, for instance whenactivating a TiN barrier/capping layer.

In a second step (b) a master electrode comprising an electricallyconducting electrode layer, of at least one inert material, such asplatinum, and an insulating pattern layer, is put in close physicalcontact with the conducting top layer, such as the seed layer, on thesubstrate in the presence of an electrolyte, forming electrochemicalcells, filled with electrolyte, defined by the cavities of theinsulating structures on the master. Putting the master in close contactwith the top layer on the substrate includes aligning the masterelectrode insulating pattern to the patterned layer on the substrate.This step can include the use of alignment marks on the front side orbackside of the master electrode that can be aligned to thecorresponding alignment marks on the substrate. The alignment procedurecan be performed before or after applying the electrolyte. Predepositedanode material may previously be arranged onto said conducting electrodelayer in the cavities of the insulating pattern layer prior to puttingthe master in contact with a substrate. Predeposited material in themaster electrode cavities can be cleaned and activated in advance, inthe same manner as described for the substrate seed layer in the firststep “(a)”, before putting the master into contact with the substrate.

Said electrolyte comprises a solution of cations and anions appropriatefor electrochemical etching and/or plating, such as conventionalelectroplating baths. For instance, when the ECPR etched or platedstructures are copper, a copper sulphate bath can be used, such as anacidic copper sulphate bath. Acidic may include a pH<4, such as betweenpH=2 and pH=4. In some embodiments, additives can be used, such assuppressors, levellers and/or accelerators, for instance PEG andchloride ions and/or SPS. In another example, when the ECPR etched orplated structures are Ni, a Watt's bath can be used. Appropriateelectrolyte systems for different materials of ECPR etched or platedstructures are described in: Lawrence J. Durney, et al, ElectroplatingEngineering Handbook, 4th ed., (1984).

In a third step (c) structures of conducting material are formed usingECPR etching or plating by applying a voltage, using an external powersource, to the master electrode and to the seed layer on the substratefor creating an electrochemical process simultaneously inside each ofthe electrochemical cells defined by the cavities of the masterelectrode and the top layer on the substrate. When the voltage isapplied in such a manner that the seed layer on the substrate is anodeand the conducting electrode layer in the master electrode is cathode,the seed layer material is dissolved and at the same time material isdeposited inside the cavities of the master electrode. The groovescreated by dissolving the seed layer separate the remaining structuresof the seed layer. The structures formed from the remaining seed layeris a negative image of the cavities of the insulating pattern layer ofthe master electrode; and these structures are referred to as “ECPRetched structures” below in this description. When the voltage isapplied in such a manner that the conducting electrode layer in themaster electrode is anode and the seed layer of the substrate iscathode, the predeposited anode material inside the cavities of themaster electrode is dissolved and at the same time material is depositedon the conducting layer on the substrate in the cavities that are filledwith electrolyte. The deposited material on the conducting layer on thesubstrate forms structures that are a positive image of the cavities ofthe insulating pattern layer of the master electrode; and thesestructures are referred to as “ECPR plated structures” below in thisdescription.

Said ECPR etched or ECPR plated structures can be comprised ofconducting materials, such as metals or alloys, for instance Au, Ag, Ni,Cu, Sn, Pb and/or SnAg, SnAgCu, AgCu and/or combinations thereof, forexample Cu.

In one embodiment, said anode material is predeposited in the cavitiesof the master electrode by using ECPR etching of a material, which isanode, and depositing said material onto the conducting electrode, whichis cathode, in the cavities of the insulating pattern layer of themaster electrode. In other embodiments, said anode material ispredeposited by regular electroplating, electroless plating, immersionplating, CVD, MOCVD, (charged) powder-coating, chemical grafting and/orelectrografting said material selectively onto the conducting electrodelayer in the cavities of the insulating pattern layer of the masterelectrode.

The voltage can be applied in a manner that improves the uniformityand/or properties of the etched and/or plated structures. The appliedvoltage can be a DC voltage, a pulsed voltage, a square pulsed voltage,a pulse reverse voltage and/or a combination thereof.

The uniformity of the etched and/or plated structures can be increasedby choosing an optimized combination of applied voltage waveform,amplitude and frequency. The etch depth or plating height can becontrolled by monitoring the time and the current passing through themaster electrode. If the total electrode area is known, the currentdensity can be predicted from the current passing through the electrodearea. The current density corresponds to an etching or plating rate andhence the etching depth or plating height can be predicted from theetching or plating rate and time.

In some embodiments, the etching or plating process is stopped bydisconnecting the applied voltage before reaching the underlying surfaceof the dissolving anode material. For the etching process, this meansthat the process is stopped when a layer is still remaining in thebottom of the etched grooves in the seed layer, covering the underlyingsubstrate layer. Otherwise, there is a risk that the electric connectionto certain portions of the seed layer may be broken. For the platingprocess, this means that the process is stopped when a layer ofpredeposited anode material still remains, such as 5% to 50%, coveringthe conducting electrode layer. Otherwise, uneven current distributionmay occur in the respective electrochemical cells.

In some embodiments, the desired height of the plated structures issignificantly less than the thickness of the predeposited anodematerial. This implies that several layers of structures can be platedonto one or several substrates before having to predeposit new anodematerial. In some examples the height of the predeposited material canbe at least twice as thick as the height of the plated structures.

In some embodiments, multiple layers of ECPR plated structures areapplied directly onto each other.

In a fourth step (d) after the ECPR etched or plated structures areformed, the master is separated from the substrate in a manner thatminimizes damages on the master or on the ECPR etched or platedstructures on the substrate. The method can be performed by holding thesubstrate in a fixed position and moving the master electrode in adirection perpendicular to the substrate surface or by holding themaster electrode in a fixed position and moving the substrate in adirection perpendicular to the master electrode surface. In otherembodiments, the separation can be performed in a less parallel mannerin order to ease the separation.

In a fifth step (e) after ECPR plating, the seed layer on the substrateis removed so that the deposited structures are not connected to eachother by the seed layer. After ECPR etching, remaining residues of theseed layer, which were not etched away, such as remaining debris orparticles or even portions of the seed layer, inside the groovesseparating the structures, can be removed. The seed layer removing stepcan include applying wet etching chemicals suitable for globally etchingthe materials that the seed layer is comprised of. An anisotropicetching method can be used in order to avoid or reduce the etching ofthe sidewalls and/or undercutting of the ECPR plated structures. In somecases the seed layer can be removed with dry-etching, for instanceion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching,laser-ablation, ion-milling. Dry-etching may remove the material byevaporation and removal in gaseous form. In some embodiments, the seedlayer can be removed by a combination of dry-etching and wet-etchingmethods. For instance, a dry-etching method can sometimes leave residuesor bi-products from etching the seed layer. These residues orbi-products can in some embodiments be removed by wet-etching methods.One example is: when dry-etching copper, a bi-product is formed whichcan be rinsed away with a wet-etch method containing hydrochloric acid.In some embodiments, said seed layer removing step can includeelectrochemical etching methods by applying a voltage making the seedlayer anode and thereby dissolving (etching) at least some portions ofsaid seed layer. Said electrochemical etching methods can in someembodiments include ECPR etching of at least some portions of the seedlayer. In some embodiments, a protective coating is applied uniformlyall over said ECPR etched or plated structures; said protective coatingis treated with an anisotropic etch, said etch having the property ofetching with a higher rate in a vertical direction than in lateraldirection such as said dry-etching methods, thereby uncovering the topof said structures and/or the seed layer between the structures whileleaving a protective layer on the side walls of said structures. In thiscase, the seed layer can be removed using said etching methods withoutetching the side walls and/or creating corner rounding of the ECPRetched or plated structures. Said protective coating can comprisematerials, and can be applied with methods, such as used for anetch-mask layer described below. Said protective coating on thesidewalls of said structures can be removed after finishing the seedlayer etching. In the case that a barrier/capping layer and/or adhesionlayer have been applied on the substrate prior to applying the seedlayer, these layers can be removed in the areas between the ECPR etchedor plated structures using the same methods as mentioned above for theseed layer. In some cases, the seed layer, barrier/capping layer and/oradhesion layer are comprised of materials that can be selectively etchedin relation to the material of the ECPR plated structures.

In some embodiments, said seed layer, barrier/capping layer and/oradhesion layer can be treated with methods converting said layers intoinsulating material. Such methods can for instance include:electrochemical anodization, such as anodizing a Ti layer to TiO₂;thermal and/or plasma based treatment in an environment including gasesor precursors, such as nitrogen and/or oxygen, that converts said layersinto insulating layers; and/or chemical treatment for instance by strongoxidizing agents, such as peroxides and/or hydroxides. In this case,said layers being converted into insulating layers do not necessarilyhave to be removed.

After the ECPR etching or plating step, remaining material depositedinside the cavities of the master electrode can be removed using thesame methods as for removing the seed layer on the substrate. Theremaining material can in some embodiments also be removed by regularplating and/or ECPR plating onto a cathode and/or dummy substrate,respectively. In some embodiments this is done prior to using the masterelectrode in another ECPR etching step or prior to predepositing newmaterial inside the cavities of the master used for the ECPR platingstep. Alternatively, during plating, only a portion of the predepositedmaterial may be used in a single procedure and another portion of thepredeposited material may be used in the next procedure, for a number ofprocedures. Alternatively, during etching, the material deposited on thecathode, i.e. the master electrode, may not need to be removed betweeneach procedure, but may be removed between each second, third, etc.,procedure.

In a sixth step (f) a dielectric layer is applied onto the top layer ofthe substrate. In some embodiments, a barrier/capping layer and/oradhesion layer are applied onto the top layer of the substrate prior toapplying said dielectric layer in order to improve the adhesionproperties and/or prevent contamination, migration (electromigration)and/or diffusion of material; said barrier/capping layer and/or adhesionlayer may be comprised of materials mentioned above and can be appliedwith methods described above. In some embodiments, said barrier/cappingand/or adhesion layer can comprise materials such as for an etch-stoplayer described below. Said dielectric layer can comprise one or severallayers of materials with low dielectric constants.

The dielectric layer can be applied by spin-coating, spray-coating,powder-coating, dip-coating, roller-coating, sputtering, PVD, CVD,Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition, byother suitable deposition processes and/or by combinations thereof. Thedielectric layer can be applied so that it completely covers the ECPRetched or plated structures as well as fills up the cavities. The layeris applied as uniformly as possible in order to avoid or minimize theuse of a planarization process.

After application, a process can be performed to uncover the top of atleast some parts of said structures from the dielectric layer. In anembodiment this is done by planarizing the dielectric layer to the samelevel as the top of said structures. Said planarization can be done bypolishing and/or etching methods. The polishing methods can bemechanical and/or chemical. In some embodiments,chemical-mechanical-polishing (CMP) can be used. CMP includesplanarizing the dielectric material using a mechanical force from arotating or translating polishing pad together with a chemical componentfrom a polishing slurry that is applied on the polishing pad which isput in close contact with the dielectric material or directly onto thematerial. The slurry chemistry is relevant for proper polishing. It canconsist of micro or nano sized silica or aluminum particles in a carriersolution. During the CMP planarization, a chemical reaction occurs atthe dielectric surface, which makes the surface susceptible tomechanical abrasion by the particles suspended in the slurry. Theabraded particles are then swept away from the vicinity of the substratesurface and flushed from the system as fresh slurry is added and usedslurry is removed from the system.

Another planarization method is to use a doctor blade.

A further planarization method is contact planarization (CP), whichcomprises applying a force or a pressure with a planar disc, which forinstance is comprised of silicon, glass and/or quartz, onto a layerthereby reducing the unevenness of the layer surface. In someembodiments, a planarizing material layer is applied onto the dielectriclayer prior to using said planarization methods. The planarizingmaterial layer results in a more planar surface, than of the underlyinglayer, when applied. Said planarizing material layer can be applied withmethods such as spin-coating, spray-coating, powder-coating,dip-coating, roller-coating, sputtering, PVD, CVD, PEVCD,electrodeposition and/or by combinations thereof. In some embodiments,the dielectric material and/or said planarization material layer is notcured prior to using said planarization methods which means that thematerial is in a more or less soft or flowable condition so that thematerial moves and planarize under the influence of the pressure. Whenusing CP methods, said planar disc can be optically transparent, andUV-light and/or heat radiation can pass there through and be applied inorder to cure said planarization material layer and/or dielectric layer.In other embodiments, the dielectric and/or planarizing material layeris brought into contact with said planar disc without applying apressure. Thereafter, the dielectric and/or planarizing material layercan be heated (for example above the glass temperature T_(g)) followedby applying a mechanical force by the planar disc onto the dielectricand/or planarizing material layer during sufficient time forplanarization to occur. The heating may occur by having the disc at anelevated temperature or heating the disc. After releasing the pressure,the dielectric and/or planarizing material layer can be cooled (forexample below T_(g)) and the planar disc can be removed from theplanarized surface.

In some embodiments, planarization using said etching methods (commonlyreferred to as etch-back methods) include dry-etching methods such asion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching,laser-ablation, ion-milling and/or combinations thereof. Said etchingmethods may give a uniform etching rate over the entire surface that isplanarized.

Planarization can in some embodiments be preformed by combiningdifferent planarization methods. In some cases it can be suitable firstto use CMP and/or CP to planarize the top surface and then use saidetching methods to further planarize or further remove said planarizingmaterial layer and/or dielectric layer until it uncovers the top of theECPR etched or ECPR plated structures. The etching may be global or onlyaffect the dielectric material. For instance, the planarization speedcan be significantly higher on the dielectric material than on the ECPRetched or plated structures. This minimizes the amount of abradedmaterial from the ECPR etched or plated structures during saidplanarization step. The structure material or metal may include anetch-stop layer or coating for preventing etching thereof. The etchingcan be continued until all structure portions are uncovered. The etchingcan be further continued in order to ensure that all structure portionsare safely uncovered, such as less than about 20% extra, for exampleless than about 10%, for instance less than about 1%.

In some embodiments, end-point detection can be used to determine whensaid etching or planarization method is completed. The end-pointdetection method can comprise the use of a sensor that detects when thematerial of the ECPR etched or plated structures is being abraded and/oretched by said planarization methods. The detection can be based oninterferometry or spectral analysis of the etching plasma that detectsmolecules or atoms of the ECPR etched or ECPR plated structures, whichare abraded/etched by said etching or planarization methods. Other enddetection methods may be used such as laser measurement of the height ofthe layer. Yet further end-point detection methods can include a sensorfor analysis of the color of the planarized material, such as by using acamera, for example an LCD-camera.

In some embodiments, the tops of at least some parts of said structuresare uncovered from the dielectric layer, which covers at least someparts of the structures, by patterning said dielectric layer with forexample a lithographic process. Said lithographic process can bephotolithography, laser lithography, E-beam lithography, nanoimprintingor other lithographic processes suitable for the dielectric material.

In another embodiment, at least some parts of the top of said structuresas delimited by an etch-mask, are uncovered by dry-etching thedielectric layer with methods such as ion-sputtering,reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation,ion-milling. The patterned material used as an etch-mask for thedry-etching process can be a photoresist and/or another polymer materialthat can be patterned by said lithographic processes. The etch-maskmaterial for dry-etching the dielectric layer can also comprisematerials such as SiN, SiO₂, SiC, tetraethyl orthosilicate (TEOS), SiON,SiOC, SICN:H, (non-porous) fluorine doped silicon glass (FSG),(non-porous) organic doped silicon glass (OSG), a low-k dielectricbarrier/etch stop film such as BLOk™ (Applied Materials), Pt, Ti, TiW,TiN, Al, Cr, Au, Ni, Cu, Ag, other metals, other hard materials and/orcombinations thereof. The etch-mask material can in turn be etched usinga patterned photoresist and/or another resist, which is patterned withsaid lithographic processes, as a mask. In some embodiments, theetch-mask can comprise at least one layer of ECPR etched or platedstructures. In some embodiment, said etch-mask is removed after theetching step. However, in other embodiments, such as when the etch-maskcomprise and insulating material, removing the etch-mask is notrequired, for instance in order to improve mechanical properties of themultilayer structure.

In some embodiments, said dielectric layer can be applied with athickness corresponding to multiple structure layers and patterned inseveral layers prior to applying at least one structure layer.Alternatively, said dielectric layer can be applied and patternedrepeatedly, thereby creating a patterned dielectric layer with athickness corresponding to multiple structure layers, prior to applyingat least one structure layer.

In all embodiments, the method for uncovering at least some parts of theECPR etched or plated structures from the dielectric material caninclude a combination of said planarization methods and said patterningmethods.

In some embodiments, the dielectric materials can be comprised ofmaterials having dielectric constants less than 4.0. Such materials aregenerally referred to as low-k materials. The low-k materials cancomprise carbon-doped dielectrics, such as OSG, FSG, organic polymers,and the like. In other embodiments, ultra-low-k dielectric materials canbe used with a k-value ranging from less than 2.5. For all embodiments,the dielectric material can be comprised of organic compounds, such aspolymers, as well as insulating inorganic compounds such as oxidesand/or nitrides. Used polymer materials can for instance be: polyimide,siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE),silicones, elastomeric polymers, E-beam resists (such as ZEP(Sumitomo)), photoresists, thinfilm resists, thickfilm resists,polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARCmaterials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxypolymers, fluoro elastomers, acrylate polymers, (natural) rubber,silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene,fluoromethylene cyanate ester, inorganic-organic hybrid polymers,(fluorinated and/or hydrogenated) amorphous carbon, by other polymersand/or by combinations thereof. Used inorganic compounds can forinstance be organic doped silicon glass (OSG), fluorine doped siliconglass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS),SiN, SiO₂, SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials,silicates, silica based materials, silsesquioxane (SSQ) based material,(nanoporous) methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ),TiO₂, Al₂O₃, TiN and/or combinations thereof.

Said dielectric material can also comprise other available low-kdielectrics listed in the publication: K. Maex, M. R. Baklanov, D.Shamiryan, F. Iacopi, S. H. Brongersma, Z. S. Yanovitskaya, J. Appl.Phys. 93, 8793 (2003).

In some embodiments, an etch-stop layer is deposited onto the top layeron the substrate prior to applying the dielectric layer. The etch-stopmaterial can be comprised of a material that is much less effected bysaid dry-etching processes than the dielectric material, and which canbe used for selectively etch cavities in the dielectric layer down tothe underlying etch-stop layer on top of underlying layer of thesubstrate or etch down the dielectric layer to slightly below the top ofthe structure layer. For instance, the etch-stop material can becomprised of SiC, SiN, Pt and/or TiW films. A low-k dielectricbarrier/etch stop film, such as BLOk™ may be used. Material used forsaid barrier/capping, adhesion and/or etch-mask layer may also be usedfor the etch-stop layer. This silicon carbide film is deposited usingtrimethylsilane ((CH₃)₃SiH) and has a lower dielectric constant (k<5)than that of conventional SiC films (k>7) generated by SiH₄ and CH₄, andthat of plasma silicon nitride (k>7). In some embodiments, saidetch-stop layer can also function as a barrier/capping layer and/oradhesion layer, which adhesion layer also may improve the adhesionbetween the lower dielectric layer and the upper dielectric layer.

In some aspects, for instance when the dielectric material is a porousultra low-k dielectric material, a pore sealing operation can be doneprior to applying any material layer onto the dielectric. In otherembodiments, said dielectric material can be a sacrificial polymermaterial wherein the sacrificial polymer is decomposed into a gaseousphase when for instance treating the material with heat or radiation. Inthis case, said dielectric material can be removed, by decomposing saidmaterial and allowing the byproducts to diffuse away, after the multiplestructure layers are formed and thereby creating voids or air gaps inthe areas that were occupied by the dielectric layer. Said sacrificialpolymer used can be a copolymer of butylnorbornene and triethoxysilylnorbornene, such as Unity Sacrificial Polymer™ (Promerus). Further more,by using mechanically stable and insulating barrier/capping and/oretch-mask layers that are not removed from the multiple structurelayers, said multiple structure layers are prevented from collapsing.

In some embodiments, forming multiple layers of conducting and/ordielectric materials includes creating at least one layer with ECPRetching and/or plating and creating at least another layer with knownmasking and deposition techniques such as lithography followed byelectrodeposition, electroless deposition, wet etching, dry etching orother methods for creating a patterned layer of a conducting material.

Below, several of the method steps for producing a multilayer substratewill be disclosed on the drawings, which show several embodiments of themethod steps.

FIGS. 1( a) to (h) illustrate the steps for producing a substratecomprising multiple layers of ECPR etched structures and multiple layersof planarized dielectric material.

FIG. 1( a) illustrates a substrate 2 onto which a seed layer 1 has beenapplied with the method in said step “(a)”.

FIG. 1( b) illustrates how the master electrode 4 is aligned to and putin contact with the seed layer 1 on the substrate 2 in the presence ofan electrolyte 3 with the method in said step “(b)”.

FIG. 1( c) illustrates how ECPR etching proceeds with the method in saidstep “(c)”. ECPR etched structures 8, which is a replica (negativeimage) of the insulating pattern layer 5 of the master electrode 4, areformed in the seed layer on the substrate 2. The etched material 7 isdeposited on the conducting electrode layer 6 in the cavities of themaster electrode. The ECPR etching process is stopped when the etchinghas removed the entire thickness of the seed layer 1. The etching can inan embodiment be stopped before or prior to etching the entire thicknessof the seed layer.

FIG. 1( d) illustrates the substrate with ECPR etched structures 8 afterseparating the master electrode 4 from the substrate 2 with the methodin said step “(d)”. Possible residues or particles or portions of theseed layer have been removed in the etched grooves. Moreover, thematerial 7 deposited inside the cavities of the master electrode hasbeen removed, such as according to the method in said step “(e)”.

FIG. 1( e) illustrates how a dielectric material 9 has been applied withthe method in said step “(f)” and covers the ECPR etched structures 8.

FIG. 1( f) illustrates how the dielectric material 9 has been planarizedwith the method in step “(f)”, uncovering the top of the ECPR etchedstructures 8.

FIG. 1( g) illustrates how a second seed layer has been applied with themethod in said step “(a)”, how ECPR etched structures 8 has been formedby etching grooves in the seed layer with the method in “(b)” to “(e)”and how a second layer of dielectric material 9 has been applied andplanarized, with the method in said step “(f)”, uncovering the top ofthe ECPR etched structures.

FIG. 1( h) illustrates how multiple layers of ECPR etched structures 8and planarized dielectric material 9 have been formed on the substrate 2by repeating said steps “(a)” to “(f)”.

If polishing is used in the planarization steps of FIGS. 1( f) and 1(h),the polishing is performed on both the hard structural material 8, suchas of metal, as well as on the soft dielectric material 9. This canresult in dishing and erosion as explained above. The dishing anderosion problems are directly related to the amount of structurematerial that is planarized. By carefully controlling the thickness ofthe structure layer, by using a master electrode with predeposited anodematerial, dishing, erosion and overall planarity problems can besignificantly reduced or even eliminated.

FIGS. 2( a) to 2(p) illustrate the steps for producing a substratecomprising multiple layers of ECPR plated structures and multiple layersof planarized dielectric material.

FIG. 2( a) illustrates a substrate 2 onto which a seed layer 1 has beenapplied with the method described in said step “(a)”.

FIG. 2( b) illustrates how the master electrode 4 is aligned to and putin contact with the seed layer 1 on the substrate 2 in the presence ofan electrolyte 3 with the method in said step “(b)”.

FIG. 2( c) illustrates ECPR plating with the method in said step “(c)”.An anode material 10, which is previously predeposited onto theconducting electrode layer 6 in the cavities formed in the insulatingpattern layer 5 of the master electrode 4, is dissolved and transportedin the electrolyte 3 at the same time as ECPR plated structures 11 areformed onto the seed layer 1 on the substrate 2 creating a pattern whichis a replica (positive image) of the cavities of the master electrode.

FIG. 2( d) illustrates the substrate 2 with ECPR plated structures 11after separating the master electrode 4 from the substrate 2 with themethod in said step “(d)” and after removing the seed layer in thecavities between the ECPR plated structures with the method described insaid step “(e)”. All or substantially all of the anode material, whichhad been predeposited in the cavities of the master, has beentransferred to the substrate forming the ECPR plated structures.Remaining residues of predeposited material in the master can be removedaccording to the methods described in said step “(e)”.

FIG. 2( e) illustrates an alternative to FIG. 2( d) showing thesubstrate with ECPR plated structures 11 after separating the master 4from the substrate 2 with the method in said step “(d)” and afterremoving the seed layer in the cavities between the ECPR platedstructures with the method described in said step “(e)”. Only a portionof the anode material 10, which had been predeposited in the cavities ofthe master, has been transferred to the substrate forming the ECPRplated structures. The remaining predeposited anode material can be usedfor one or several subsequent ECPR plating steps or it can be removedfrom the cavities by using the methods described in said step “(e)”. Insome embodiments, the remaining anode material does not need to beremoved before predepositing new anode material for using in asubsequent ECPR plating step.

FIG. 2( f) illustrates how a dielectric material 9 has been applied withthe method in said step “(f)” and covering the ECPR plated structures 11on a substrate 2.

FIG. 2( g) illustrates how the dielectric material 9 has been planarizedwith the method in said step “(f)”, uncovering the top of the ECPRplated structures 11 on the substrate 2. If a polishing method is used,the polishing will be performed on structures having different hardness,such as the hard structure layer, such as of metal and the soft materiallayer of dielectric material. This can result in dishing and erosion ofthe soft material and crack formation on the structure layer. Thedishing and erosion problems are directly related to the amount ofstructure material that is planarized. By carefully controlling thethickness of the structure layer, by using a master electrode withpredeposited anode material, dishing, erosion and overall planarityproblems can be significantly reduced or even eliminated.

FIG. 2( h) illustrates how a second seed layer 1 has been applied withthe method in said step “(a)” and how a second layer of ECPR platedstructures 11 is formed by plating a pattern, which is a replica of thecavities of the master electrode, onto the seed layer 1 with the methodsin said steps “(b)” to “(e)”.

FIG. 2( i) illustrates how the seed layer in the cavities between theECPR plated structures is removed with the method described in said step“(e)”.

FIG. 2( j) illustrates how a dielectric material 9 has been applied withthe method in said step “(f)” and covering the ECPR plated structures 11on substrate 2.

FIG. 2( k) illustrates how the dielectric material 9 has been planarizedwith the method in said step “(f)”, uncovering the top of the ECPRplated structures 11 on the substrate 2.

FIG. 2( l) illustrates how a third seed layer 1 has been applied withthe method in said step “(a)” and how ECPR plated structures 11 has beenformed by plating a pattern, which is a replica of the cavities of themaster electrode, onto the seed layer 1 with the methods in said steps“(b)” to “(e)”.

FIG. 2( m) illustrates how a fourth layer of ECPR plated structures 11is formed onto at least some parts of the previously plated patternwithout having removed the previously applied seed layer 1. The masterelectrode 4 is aligned to and put in contact with the underlying patternwith the methods in said step “(b)” in a way that the cavities of theinsulating layer 5, which are enclosing the electrolyte 3, are placedonly in the areas which are to be plated upon. When the plating voltageis applied, the predeposited anode material 10 is dissolved from theconducting electrode layer 6 in the cavities of the master and ECPRplated structures 11 are formed by the method described in said step“(c)”. This step can only be performed if at least some parts of thefourth structure layer are completely inside the structure layer of theprevious layer, and results in a saving of method steps.

FIG. 2( n) illustrates a substrate 2 onto which a fourth layer of ECPRplated structures 11 have been deposited directly onto at least someparts of the second ECPR plated pattern without removing the seed layer1 which had been applied prior to forming the third layer of ECPR platedstructures.

FIG. 2( o) illustrates how the seed layer has been removed with themethod in said step “(e)” and how a further layer of dielectric material9 has been applied and covering the ECPR plated structures 11 onsubstrate 2.

FIG. 2( p) illustrates how the dielectric material 9 has been planarizedusing the method in step “(f)” uncovering the top of the ECPR platedstructures 11.

If a polishing method is used, the polishing will be performed on twolayers having different hardness, such as the hard structure layer ofmetal and the soft material layer of dielectric material. This canresult in dishing and erosion of the soft material and crack formationon the structure layer. The dishing and erosion problems are directlyrelated to the amount of structure material that is planarized. Bycarefully controlling the thickness of the structure layer, by using amaster electrode with predeposited anode material, dishing, erosion andoverall planarity problems can be significantly reduced or eveneliminated.

FIGS. 3( a) to 3(k) illustrate the steps for producing a substratecomprising multiple layers of ECPR etched structures and multiple layersof lithography patterned dielectric material. In this embodiment,several procedure steps are saved because the dielectric material isformed with a thickness corresponding to two layers at the same time. Inaddition, two structure layers are formed in a single process, thussaving further time, by applying a seed layer of a thicknesscorresponding to two layers.

FIG. 3( a) illustrates a substrate 2 on which a seed layer 1 is arrangedwith the method in said step “(a)”.

FIG. 3( b) illustrates a master electrode 4 that is aligned and put intocontact with a seed layer 1 on a substrate 2 using the methods in saidstep “(b)” and where an electrolyte 3 is enclosed in the cavities of theinsulating layer 5 of the master.

FIG. 3( c) illustrates how ECPR etched structures are formed in the seedlayer 1 on a substrate 2 by using the methods described in said step“(c)”. The etched material 7 is transferred in the electrolyte 3 anddeposited onto the conducting electrode layer 6 in the cavities of theinsulating layer 5 in the master electrode 4.

FIG. 3( d) illustrates a substrate 2 with ECPR etched structures 8 afterseparating the master 4 from the substrate with the method in said step“(d)” and after removing possible residues or particles of the seedlayer 1 in the etched grooves. Also the material deposited inside thecavities of the master electrode has been removed according to themethod in said step “(e)”.

FIG. 3( e) illustrates how a dielectric material 9 has been applied to asubstrate 2 with the method in step “(f)” and is covering the ECPRetched structures 8. The material is applied in a thicknesscorresponding to two layers. Several of the above mentioned methods forapplying a dielectric layer, such as spin-coating or spray-coating, cangive a substantially planar surface without recesses being formed.Alternatively, a planarization material layer can be applied asdescribed in step “(f)”. However, small valleys may still be formedopposite the cavities in the structure layer 8 below. Such small valleysdo not mean any problem in this process. If necessary, the dielectricmaterial layer is planarized with for example contact planarization.Alternatively, polishing methods can be used, since a single material isaffected, namely the material of the dielectric layer. In some cases,contact planarization and/or polishing methods can be combined with saidetch-back methods to achieve desired planarization.

FIG. 3( f) illustrates how the dielectric material 9 is patterned bylithographic methods in said step “(f)”, uncovering the top of at leastsome parts of the ECPR etched structures 8 previously formed on thesubstrate 2.

FIG. 3( g) illustrates a second seed layer 1 that is applied using themethods in said step “(a)” onto the lithography patterned dielectricmaterial 9 which previously is applied to the substrate 2. The secondseed layer is applied with a thickness sufficient for two layers. Insome cases, the cavities of the dielectric material below cause theformation of grooves on top of the applied seed layer corresponding tothe pattern, as shown in the figure. Such grooves do not cause anyproblem for the present process. As mentioned above, electroplatingmethods including the used of additives, such as mentioned above, and/orpulse plating can be used to apply the relatively thick seed layer witha uniform upper surface independent on any recesses in the underlyinglayer. Using any application method, a uniform upper surface can beachieved independent on any recess in the substrate if the thickness ofthe seed layer is significantly larger than the depth of the recess.

FIG. 3( h) illustrates how the grooves of the seed layer 1 is removed,if desired, with the planarization methods such as for a dielectricmaterial which is described in said step “(f)”. Since the planarizationworks on a single material, in this case the hard material of the seedlayer, any polishing method can be used. As mentioned above, thisplanarization can in some cases be left out.

FIG. 3( i) illustrates how the master electrode 4 is aligned and put incontact with the second seed layer 1 using the methods in said step“(b)”. Electrolyte 3 is enclosed in the cavities of insulating patternlayer 5. The figure also illustrates how structures are formed by ECPRetching according to the method in said step “(c)”, whereby the etchedmaterial 7 is being deposited on the conducting electrode layer 6 in thecavities of the master electrode.

FIG. 3( j) illustrates how a second layer of ECPR etched structures 8 isformed after separating of the master electrode from the substrate 2using the method in said step “(d)” and after removing possible residuesof seed layer in the grooves of the ECPR etched structures using themethod in said step “(e)”.

FIG. 3( k) illustrates a second dielectric material 9 that is appliedwith a thickness of two layers and patterned with lithography on thesecond layer of ECPR etched structures 8 using the methods in said step“(f)”.

FIG. 3( l) illustrates how a third seed layer 1 is applied, with athickness of two layers, with the method in “(a)”, how ECPR etchedstructures 8 is formed by repeating the methods in said steps “(b)” to“(e)” and how a dielectric material 9 is applied and further patternedwith lithography using the method in said step “(f)”. These processesare repeated until the entire structure is built.

FIGS. 4( a) to 4(m) illustrate the steps for producing a substratecomprising multiple layers of ECPR plated structures and multiple layersof lithography patterned dielectric material.

FIG. 4( a) illustrates a substrate 2 onto which a relatively thin seedlayer 1 is applied with the method described in said step “(a)”.

FIG. 4( b) illustrates how the master electrode 4 is aligned and put incontact with the seed layer 1 on the substrate 2 in the presence of anelectrolyte 3, which is enclosed in the cavities of the insulatingpattern layer 5, with the method in said step “(b)”.

FIG. 4( c) illustrates how ECPR plating proceeds with the method in saidstep “(c)”. An anode material 10, which is previously predeposited ontothe conducting electrode layer 6 in the cavities exerted by theinsulating pattern 5 of the master electrode 4, is dissolved andtransported in the electrolyte 3 at the same time as ECPR platedstructures 11 are formed onto the seed layer 1 on the substrate 2creating a pattern which is a replica (positive image) of the cavitiesof the master electrode.

FIG. 4( d) illustrates the substrate 2 with ECPR plated structures 11after separating the master electrode 4 from the substrate 2 with themethod in said step “(d)”. The seed layer in the cavities between theplated structures is removed with the method described in said step“(e)”. All or substantially all of the anode material, which ispredeposited in the cavities of the master, is transferred to thesubstrate forming the ECPR plated structures. Remaining residues ofpredeposited material in the master is removed according to the methodsdescribed in said step “(e)”.

FIG. 4( e) illustrates an alternative to FIG. 4( d) showing thesubstrate with ECPR plated structures 11 after separating the masterelectrode 4 from the substrate 2 with the method in said step “(d)” andafter removing the seed layer in the cavities between the platedstructures with the method described in said step “(e)”. Only a portionof the anode material 10, which is predeposited in the cavities of themaster, is transferred to the substrate forming the ECPR platedstructures. The remaining predeposited anode material can be used forone or several subsequent ECPR plating steps or can be removed from thecavities by using the methods described in said step “(e)”. In someembodiments, the remaining anode material does not have to be removedbefore predepositing new anode material for using in a subsequent ECPRplating step.

FIG. 4( f) illustrates how a dielectric material 9 has been applied withthe method in said step “(f)” and covering the ECPR plated structures 11on a substrate 2 and having a height corresponding to two layers. Thedielectric material layer can be planarized if required.

FIG. 4( g) illustrates how the dielectric material 9 is patterned bysaid lithography and/or etching methods in step “(f)”, uncovering thetop of at least some parts of the ECPR plated structures 11 previouslyformed on the substrate 2.

FIG. 4( h) illustrates a relatively thin seed layer 1 that is appliedusing the method in said step “(a)” onto the dielectric material 9.

FIG. 4( i) illustrates a master electrode 4 that is aligned and put incontact with the seed layer 1 using the methods in said step “(b)”. Byusing the method in said step “(c)”, a second layer of ECPR platedstructure 11 is formed inside the cavities of the insulating patternlayer 5 as well as in the cavities of patterned dielectric material 9 bydissolving the predeposited anode material 10 which is transported inthe electrolyte 3 and deposited on the seed layer. At the same time, athird layer is formed by deposition. The third layer can include withsmall recesses opposite the cavities in the second dielectric layer, asshown. Such recesses normally mean no problem in the process. Recessescan also be minimized by the use of pulse-plating, such aspulse-reverse-plating, and/or by including additives in the electrolytesuch as mentioned above. If necessary, the recesses can be removed by aplanarization operation, which can be a polishing operation since onlyhard material is encountered, namely the deposited material, such as ametal.

FIG. 4( j) illustrates a third layer of ECPR plated structures 8 beingfinalized after separation of the master electrode using the method insaid step “(d)”. The seed layer is removed in the areas between the ECPRplated structures using the method in said step “(e)”. The second layerof ECPR plated structures fill up the cavities of the lithographypatterned dielectric material 9 and connect to the first layer ofunderlying structures and forms at the same time a third structurelayer.

FIG. 4( k) illustrates a second layer of dielectric material 9 that isapplied with a thickness of two layers and patterned with lithographyand/or etching on a second layer of ECPR etched structures 8 using themethods in said step “(f)”.

FIG. 4( l) illustrates how a fourth and fifth layer of ECPR platedstructures 11 are formed by repeating the methods in step “(a)” to“(e)”. At lest some portion of the ECPR plated structures connect to atleast some parts of the underlying structures through the cavities ofthe lithography patterned dielectric material 9.

FIG. 4( m) illustrates how a further layer of dielectric material 9 witha thickness of two layers is applied and patterned on the third layer ofECPR plated structures 11 using the method in said step “(f)”.

The process is repeated until the desired number of layers is built.

FIGS. 5( a) to 5(l) illustrate the steps for producing a substratecomprising multiple layers of ECPR plated structures includingbarrier/capping layers and multiple layers of lithography patterneddielectric material.

ECPR plating can be used for creating metallic interconnects insemiconductor device. A substrate 2 is patterned with a pre-metaldielectric 12, which is arranged covering possible semiconductors ortransistors formed in the substrate. The cavities or the pattern arefilled for creating connection plugs 13 of a suitable material, forinstance tungsten. A first barrier/capping layer 14 is applied onto theconnection plugs 13 and the pre-metal dielectric layer 12. Thebarrier/capping layer can be of the same materials and can be appliedwith the same methods as described for the barrier/capping layers insaid step “(f)”. On top of the barrier/capping layer, a first layer ofdielectric material 9 is applied with methods in said step “(f)”. Thedielectric material may comprise a suitable low-k or ultra low-kmaterial, also described in said step “(f)”. The result of performingthe mentioned steps is shown in FIG. 5( a).

FIG. 5( b) illustrates an etch-mask 15 that is applied and patterned ontop of the dielectric material 9. In some embodiment, said etch-mask isremoved after the etching step. However, in other embodiments, such aswhen the etch-mask comprise and insulating material, removing theetch-mask is not required, for instance in order to improve mechanicalproperties of the multilayer structure.

FIG. 5( c) illustrates how the dielectric material 9 and thebarrier/capping layer 14 are patterned by the lithography and/or etchingmethods in said step “(f)” thereby uncovering the top of the connectionplugs 13 forming cavities down to the connection plug 13.

FIG. 5( d) illustrates how a barrier/capping layer 14 and a seed layer 1is applied onto, and into the cavities of, the patterned dielectricmaterial 9 using the method in said step “(a)”. The barrier/cappinglayer can also functions as a seed layer, e.g. when using a Ru layer.

FIG. 5( e) illustrates how a master electrode 4 is aligned to thepatterned dielectric material 9 and put in contact with the seed layer 1and enclosing electrolyte 3 in the cavities of the insulating patternlayer 5 using the method in step “(b)”. When applying a voltage thepredeposited anode material 10 is dissolved at the conducting electrodelayer 6 and ECPR plated structures are deposited on the seed layer 1 inthe cavities that are filled with electrolyte 3, as described in themethod in said step “(c)”.

FIG. 5( f) illustrates how two layers of ECPR plated structures 11 areformed in one step where the first is filling the cavities of thedielectric material 9 and the second is forming lines on top of someparts of the dielectric material 9. Alternatively, the via can first befilled by ECPR plating using the methods in said steps “(b)” to “(d)”and then ECPR plated structures 11 are deposited on top on the via layerby repeating the methods in said steps “(b)” to “(d)” and withoutremoving the seed layer in between, possibly by using a second masterelectrode with a different pattern.

FIG. 5( g) illustrates how the seed layer and the barrier/capping layerselectively are removed in the areas between the ECPR plated structures11 using the method in said step “(e)”. An anisotropic etching methodcan be used in order to avoid or reduce the etching of the sidewallsand/or undercutting of the ECPR plated structures 11. The seed layerand/or the capping layer can be of a material that can be selectivelyetched in relation to the material of the ECPR plated structures 11.Alternatively, said seed layer and/or barrier/capping layer can betreated with methods, such as anodization methods mentioned above,converting said materials into insulating materials. In this case,removing said layers may not be required.

FIG. 5( h) illustrates how a barrier/capping coating 16 selectively isapplied on the ECPR plated structures. Moreover, a second layer ofdielectric material 9 is applied with a thickness of two layers andpatterned with lithography, using the method in said step “(f)”. Thedeposition of this barrier/capping coating can be done with a methodthat selectively deposits the material only onto the ECPR platedconductive structures as described in the method in said step “(f)” anddoes not deposit material on the non-conductive dielectric material 9.The deposition process can for instance be an electroless depositionprocess mentioned below and the material can for instance be CoWP, CoWBor CoWBP. In some embodiments, the barrier/capping coating is removed,using said etching methods, in the bottom of the cavities of the applieddielectric layer 9 in order to achieve a better contact to a subsequentstructure layer.

FIG. 5( i) illustrates how a barrier/capping layer 14 and a seed layer 1is applied on top of and into the cavities of the patterned dielectricmaterial 9, using the method in said step “(a)”.

FIG. 5( j) illustrates how the cavities of the dielectric material 9 isfilled and how another wire layer of ECPR plated structures 11 issimultaneously formed on top of the dielectric material by repeating themethods in said steps “(b)” to “(d)”. The seed layer and thebarrier/capping layer are selectively removed in the areas between theECPR plated structures 11 using the method in said step “(e)”. Abarrier/capping coating 16 is selectively applied onto the ECPR platedstructures and a dielectric material is applied and patterned, using themethod in said step “(f)”.

FIG. 5( k) illustrates the result after applying a barrier/capping layer14 and a seed layer 1 using the method in said step “(a)”; forming ECPRplated structures that fill up the cavities of the patterned dielectricmaterial 9 and forming a wire layer of ECPR plated structures 11 on topof the dielectric material by repeating the methods in said steps “(b)”to “(d)”; and removing the barrier/capping layer and seed layer from theareas between the ECPR plated structures using the method in said step“(e)”.

FIG. 5( l) illustrates how another layer of barrier/capping coating 16is applied onto the ECPR plated structures 11 and how a dielectricmaterial 9 is applied and patterned and/or planarized to uncover the topof the plated structures using the method in said step “(f)”.

Finally, a passivation layer 17 is applied on top of the ECPR platedstructures and dielectric material 9. The passivation layer can be oneor several barrier/capping layers and/or dielectric material layers.

FIGS. 6( a) to 6(n) illustrate the steps for producing a substratecomprising multiple layers of ECPR plated structures includingbarrier/capping layers and multiple layers of planarized dielectricmaterial.

FIG. 6( a) illustrates a substrate 2 with a patterned pre-metaldielectric layer 12 and connection plugs 13, onto which abarrier/capping layer 14 and a seed layer 1 has been applied using themethod in said step “(a)”. The substrate is similar to the substrateshown in FIG. 5( a).

FIG. 6( b) illustrates how a master electrode 4 is aligned to the toplayer on the substrate and put in contact with the seed layer 1 andenclosing electrolyte 3 in the cavities of the insulating pattern layer5 using the method in said step “(b)”. When applying a voltage, thepredeposited anode material 10 is dissolved at the conducting electrodelayer 6 and ECPR plated structures are deposited on the seed layer 1 inthe cavities that are filled with electrolyte 3, as described in themethod in said step “(c)”.

FIG. 6( c) illustrates how ECPR plated structures 11 is formed as areplica (positive image) of the cavities of the master electrode that isseparated from the substrate using the method in said step “(d)”.

FIG. 6( d) illustrates how the seed layer 1 and the barrier/cappinglayer 14 are removed between the ECPR plated structures 11. Ananisotropic etching method can be used in order to avoid or reduce theetching of the sidewalls and/or undercutting of the ECPR platedstructures 11. The seed layer and/or the barrier/capping layer can be ofa material that can be selectively etched in respect to the material ofthe ECPR plated structures 11.

FIG. 6( e) illustrates how a barrier/capping coating 16 selectively isapplied and is covering the ECPR plated structures 11. Thebarrier/capping coating 16 can also form an etch-stop coating asdescribed below.

FIG. 6( f) illustrates how a dielectric material 9 is applied andplanarized. The planarization is performed by a polishing action untilthe dielectric layer is slightly above the structure below as shown inFIG. 6( f). This planarization is performed on a single material, namelythe soft material of the dielectric layer.

FIG. 6( g) illustrates a final removal of dielectric material until thetop of the structure below is uncovered. The final removal can beperformed by etching with a method that removes the material with auniform rate. If the coating 16 has etch-stop properties, the etchingonly affects the dielectric material. The material is removed until thestructure material 8 below is uncovered. The removal can continue forsome time to form a safety margin, for example remove 5 to 10% extramaterial of the dielectric material, calculated from the start of theetch process. If necessary, the barrier/capping coating 16 can beselectively removed from the top of the exposed structure, especially ifthe coating 16 is an etch-stop coating.

FIG. 6( h) illustrates how a second layer of ECPR plated structures 11is formed using the methods in said steps “(b)” to “(d)”; and how theseed layer 1 and the barrier/capping layer 14 is removed between thesecond ECPR plated structures using the method in said step “(e)”; andhow a barrier/capping coating 16 selectively is applied and is coveringthe ECPR plated structures; and how a second layer of dielectricmaterial 9 is applied and planarized using the method in said step “(f)”uncovering the top of the ECPR plated structures as described above.

FIG. 6( i) illustrates how a barrier/capping layer 14 and a seed layer 1are applied using the method in said step “(a)”; and how a subsequentlayer of ECPR plated structures 11 is formed onto the seed layer usingthe methods in said steps “(b)” to “(d)”.

FIG. 6( j) illustrates how a subsequent layer of ECPR plated structuresis formed, using the methods in said steps “(a)” to “(d)”, directly ontoat least some parts of the previous plated structures without removingthe previously applied barrier/capping layer 14 and seed layer 1. Thefigure illustrates how the master electrode 4 is aligned and put incontact with the previously formed ECPR plated structures using themethod in said step “(b)”. When a voltage is applied over the masterelectrode and the seed layer, the predeposited anode material 10 isdissolved and transported in the electrolyte 3 inside the cavities ofthe insulating pattern layer 5 and a subsequent layer of ECPR platedstructures is formed, onto at least some parts of the previous layer ofECPR plated structures.

FIG. 6( k) illustrates how a subsequent layer of ECPR plated structures11 is formed, with the method in said steps “(a)” to “(d)”, onto atleast some parts of the preceding layer of ECPR plated structureswithout removing the preceding barrier/capping layer 14 and seed layer1.

FIG. 6( l) illustrates how the seed layer 1 and the barrier/cappinglayer 14 are removed selectively between the ECPR plated structuresusing the method in said step “(e)”; how a barrier/capping coatingselectively is applied to and is covering both the previous and thesubsequent layer the ECPR plated structures 11 and how another layer ofdielectric material 9 is applied and planarized to uncover the top ofthe previous layer of ECPR plated structures, using the method in saidstep “(f)”.

FIG. 6( m) illustrates how a barrier/capping layer 14 and a seed layer 1is applied using the method in said step “(a)”; a subsequent layer ofECPR plated structures 11 is formed onto the seed layer 1 using themethods in said steps “(b)” to “(d)”; and how the barrier/capping layer14 and seed layer 1 are removed selectively between the ECPR platedstructures using the method in said step “(e)”.

FIG. 6( n) illustrates how a barrier/capping coating 16 selectively isapplied to and is covering the ECPR plated structures 11 and how anotherlayer of dielectric material 9 is applied and planarized using themethod in said step “(f)”.

Finally, a passivation layer 17 is applied to cover the dielectricmaterial and the top of the ECPR plated structures, which are coveredwith a barrier/capping coating. In some embodiments, forming multiplemetallic interconnect layers and dielectric layers in a semiconductordevice includes creating at least one layer of ECPR plated structuresand dielectric material, as illustrated in FIG. 5 and FIG. 6, usingeither etching or plating or a combination thereof, and creating atleast another layer of conducting structures and dielectric materialusing known lithographical and plating techniques such as the dualdamascene or single damascene process.

Some embodiments, such as when forming metallic interconnects forintegrated circuits (IC), includes fabricating said interconnects byforming multiple ECPR plated structure layers, for instance comprisingCu, and arranging a dielectric material, such as a low-k material,between said structures. In said known damascene process, thedielectrics layers are firstly etched and subsequently interconnects areelectroplated filling the cavities etched. In order to decrease theRC-delay of an IC device, dielectric materials with lower dielectricconstant is required. However, with ultra low-k dielectric material,etching and post-etch-cleaning may result in various problems such astoo high line width variations and k-value increase. As described above,the method of the present process can eliminate or reduce the number ofetching steps of said layers of dielectric material, for instance ultralow-k dielectric layers. Said elimination or reduction of number ofetching steps results in less line width variations and less k-valueincrease which enables the use of ultra low-k materials in an IC deviceand hence a lower RC-delay as well as less RC-delay variations can beachieved.

ECPR plating can be used to fill vias or other grooves in a substrateand/or in a patterned material onto a substrate.

FIG. 7( a) illustrates a via-substrate comprising a substrate 2, apatterned dielectric material 9 and a seed layer 1. A master electrodeis aligned and put in contact with the seed layer, using the methods insaid step “(b)”, in such a way that the walls of the insulating patternlayer 5 which define the cavities of the master electrode 4 are placedoutside of the lateral extent of the vias in the dielectric material 9,the cavities of the master electrode having a larger width than thevias. The predeposited anode material 10 is transferred in theelectrolyte 3 by ECPR plating using the method in said step “(c)”.

FIG. 7( b) illustrates how the cavities of the dielectric material 9 arefilled with ECPR plated structures 11. The material deposited on top ofthe seed layer beside the via can include a groove as shown in FIG. 7(b). However, the groove is in some cases of no or less importance. Byusing certain chemicals in the electrolyte, the formation of such agroove can be completely or partly eliminated. Such chemicals caninclude additive systems such as described above. Moreover, the groovescan be reduced by using pulse plating methods such as pulse reverseplating.

FIGS. 8( a) to 8(b) illustrate the steps for filling the vias of asubstrate with a patterned dielectric material when aligning thecavities of the master electrode edge to edge with the via-holes, thecavities of the master electrode having the same width as the via-holes.

FIG. 8( a) illustrates how the master electrode is aligned and put incontact with the seed layer, using the methods in said step “(b)”, insuch way that the walls of the insulating pattern layer 5 which definethe cavities of the master electrode 4 are placed “edge to edge” of thewalls of the vias in the dielectric material 9. The predeposited anodematerial 10 is transferred in the electrolyte 3 by ECPR plating usingthe method in said step “(c)”.

FIG. 8( b) illustrates how the cavities of the dielectric material 9 arefilled with ECPR plated structures 11.

FIGS. 9( a) to 9(c) illustrate the steps for filling the vias of asubstrate with a patterned dielectric material when aligning thecavities of the master electrode within the lateral extent of thevia-holes, the cavities of the master electrode having a smaller widththan the via-holes.

FIG. 9( a) illustrates how the master electrode is aligned and put incontact with the seed layer, using the method in said step “(b)”, insuch way that the walls of the insulating pattern layer 5 which definethe cavities of the master electrode 4 are placed within the lateralextent of the vias in the dielectric material 9. The predeposited anodematerial 10 is transferred in the electrolyte 3 by ECPR plating usingthe method in said step “(c)”, as shown in FIG. 9( a).

FIG. 9( b) illustrates how the cavities of the dielectric material 9 arefilled with ECPR plated structures 11.

FIG. 9( c) illustrates how the ECPR plated structures 11 are formedabove the dielectric material layer as a replica (positive image) of thecavities of insulating pattern layer on the master electrode.

FIGS. 10( a) to 10(c) illustrate the steps for forming a filledthrough-hole-substrate by filling a via-hole-substrate and planarizingthe backside.

FIG. 10( a) illustrates how a master electrode 4 is aligned and put incontact with a seed layer 1 on a substrate 2 patterned with via-holecavities. The walls of the cavities of the insulating pattern layer 5can be placed within or outside the lateral extent of, or edge to edgewith the walls of the cavities of the substrate. When a voltage isapplied, predeposited anode material 10 is dissolved at the conductingelectrode layer 6 and ECPR plated structures are formed onto the seedlayer 1 in the cavities that comprise the electrolyte 3.

FIG. 10( b) illustrates how the cavities of the substrate 2 are filledwith ECPR plated structures 11.

FIG. 10( c) illustrates how the seed layer on the front side is removed,the backside of the substrate 2 has been planarized and how the bottomof the ECPR plated structures 11 is uncovered by etching, planarizationand/or grinding from the backside.

FIGS. 11( a) to 11(c) illustrate the steps for forming a filledthrough-hole-substrate by filling a through-hole-substrate with a seedlayer on the backside.

FIG. 11( a) illustrates how a master electrode 4 is aligned and put incontact with the front side of a substrate 2 patterned with through-holecavities and a seed layer 1 on the backside. The walls of the cavitiesof the insulating pattern layer 5 can be placed within (as illustratedin this figure), or outside the lateral extent of, or edge to edge withthe walls of the cavities of the substrate. When a voltage is applied,predeposited anode material 10 is dissolved at the conducting electrodelayer 6 and ECPR plated structures are formed onto the seed layer 1 inthe cavities that comprise the electrolyte 3.

FIG. 11( b) illustrates how the cavities of the substrate 2 are filledwith ECPR plated structures 11.

FIG. 11( c) illustrates how the seed layer on the backside is removedand how the bottom of the ECPR plated structures 11 is uncovered.

FIGS. 12( a) to 12(b) illustrate the steps for forming a filledthrough-hole-substrate by filling a through-hole-substrate onto which aseed layer has been applied.

FIG. 12( a) illustrates how a master electrode 4 has been aligned andput in contact with a seed layer 1 on a substrate 2 patterned withvia-through-hole cavities whereby the seed layer 1 extends on thefront-side and on the walls of the via-through-holes. The walls of thecavities of the insulating pattern layer 5 can be placed within (asillustrated in this figure), or outside the lateral extent of, or edgeto edge with the walls of the cavities of the substrate. When a voltageis applied, predeposited anode material 10 is dissolved at theconducting electrode layer 6 and ECPR plated structures are formed ontothe seed layer 1 in the cavities that comprise the electrolyte 3.

FIG. 12( b) illustrates how the cavities of the substrate 2 are filledwith ECPR plated structures 11 and how the seed layer is removed on thefront side.

FIGS. 13( a) to 13(c) illustrate the steps for forming a filledthrough-hole-substrate including filling a via-hole-substrate that iscoated with a dielectric material and including patterning the substratebackside.

FIG. 13( a) illustrates how a master electrode 4 has been aligned andput in contact with a seed layer 1 on a substrate 2 patterned withvia-hole cavities, which in turn have been patterned by a dielectricmaterial 9 which covers the substrate front-side and the vertical wallsof the vias. The walls of the cavities of the insulating pattern layer 5can be placed within (as illustrated in this figure), or outside thelateral extent of, or edge to edge with the walls of the cavities of thesubstrate. When a voltage is applied, predeposited anode material 10 isdissolved at the conducting electrode layer 6 and ECPR plated structuresare formed onto the seed layer 1 in the cavities that comprise theelectrolyte 3.

FIG. 13( b) illustrates how the cavities of the substrate 2, which arecoated with a patterned dielectric material 9, are partly filled withECPR plated structures 11.

FIG. 13( c) illustrates how the seed layer on the front side is removedand how the backside of the substrate 2 is patterned to uncover thebottom of the ECPR plated structures 11 and the dielectric material 9.

FIGS. 14( a) to 14(c) illustrate the steps for forming a filled andfront side patterned through-hole-substrate.

FIG. 14( a) illustrates how a master electrode 4 is aligned and put incontact with a seed layer 1 on a substrate 2 patterned with via-holecavities, which in turn have been patterned by a dielectric material 9.The walls of the cavities of the insulating pattern layer 5 can beplaced within or outside (as illustrated in this figure) the lateralextent of, or edge to edge with the walls of the cavities of thesubstrate. Some parts of the cavities of the insulating pattern layer 5can be located in areas, separate from the substrate cavities, whereECPR plated structures also are to be formed. When a voltage is applied,predeposited anode material 10 is dissolved at the conducting electrodelayer 6 and ECPR plated structures are formed onto the seed layer 1 inthe cavities that comprise the electrolyte 3.

FIG. 14( b) illustrates how the cavities of the substrate 2, which arecoated with a patterned dielectric material 9, are filled and how ECPRplated structures 11 also are formed on some parts of the seed layer 1.

FIG. 14( c) illustrates how the seed layer on the front side is removedin the areas between the ECPR plated structures 11 and how the backsideof the substrate 2 is patterned to uncover the bottom of the ECPR platedstructures.

FIGS. 15( a) to 15(c) illustrate the steps for coating a patternedsubstrate, which is covered with a seed layer, with ECPR platedstructures.

FIG. 15( a) illustrates how a master electrode 4 has been aligned andput in contact with a seed layer 1 on a substrate 2 patterned withstructures. The structures exerting the pattern on the substrate can forinstance be a conducing pattern 18, a substrate pattern and/or adielectric material pattern 9. The master electrode can be placed in away that the cavities of the insulating pattern layer 5 enclose at leastsome parts of the substrate structures. Some parts of the cavities ofthe insulating pattern layer 5 can be located in areas, separate fromthe substrate structures, where ECPR plated structures also are to beformed. When a voltage is applied, predeposited anode material 10 isdissolved at the conducting electrode layer 6 and ECPR plated structuresare formed onto the seed layer 1 in the cavities that comprise theelectrolyte 3.

FIG. 15( b) illustrates how the substrate structures that were enclosedin the cavities of insulating pattern layer of the master electrode arecoated with ECPR plated structures 11. Also, other areas correspondingto the cavities of the insulating pattern layer of the master electrodethat do not enclose the substrate structures, are patterned with ECPRplated structures.

FIGS. 16( a) to 16(d) illustrate the steps for creating multiple coatinglayers on a substrate patterned with conducting material.

FIG. 16( a) illustrates how a master electrode 4 is aligned and put incontact with a seed layer onto which conducting material structures areformed 18. The master electrode can be placed in a way that the cavitiesof the insulating pattern layer 5 enclose at least some parts of theconducting material structures 18. When a voltage is applied,predeposited anode material 10 is dissolved at the conducting electrodelayer 6 and ECPR plated structures are formed onto the seed layer andthe conducting material structures 18 in the cavities that comprise theelectrolyte 3.

FIG. 16( b) illustrates how the conducting material structures 18 thatare enclosed in the cavities of the master electrode are coated withECPR plated structures 11.

FIG. 16( c) illustrates how a second coating of ECPR plated structures11 is applied to the previously coated material 19 covering theconducting material structures 18.

FIG. 16( d) illustrates how the seed layer selectively is removed in theareas between the coated structures. This method can be repeated one orseveral times whereby one or several layers of ECPR plated structures 11can be coated onto the previously coated material 19 on the conducingmaterial 18 structures. The different layers of ECPR plated structurescan be of the same or several different materials. In one embodiment,the conducting material 18 can be Cu, the first coated material 19 canbe Ni and the second coating of ECPR plated structures 11 can be Au. Inanother embodiment, the conducing material 18 can be Cu, the firstcoated material 19 can be Sn and the second coating of ECPR platedstructures 11 can be Ag. In some embodiments, the ECPR plated structuresthat coat the substrate pattern comprises a barrier/capping material,adhesion material, etch-mask material and/or etch-stop material.

FIGS. 17( a) to 17(h) are sectional views of different exemplarycombinations of designs and materials of a master electrode.

FIG. 17( a) illustrates a sectional view of a master electrodecomprising a flexible conducting foil 20 and an insulating pattern layer5.

FIG. 17( b) illustrates a sectional view of a master electrodecomprising a conducting electrode layer 6 and an insulating patternlayer 5.

FIG. 17( c) illustrates a sectional view of a master electrodecomprising a mechanical support layer 22, a conducting electrode layer 6and an insulating pattern layer 5.

FIG. 17( d) illustrates a sectional view if a master electrodecomprising a mechanical support layer 22, a conducting electrode layer6, an insulating pattern layer 5 and a flexible elastomer layer 21.

FIG. 17( e) illustrates a sectional view of a master electrodecomprising a flexible conducting foil 20, an insulating pattern layer 5and a flexible elastomer layer 21.

FIG. 17( f) illustrates a sectional view of a master electrodecomprising a conducting electrode layer 6 an insulating pattern layer 5and a flexible elastomer layer 21.

FIG. 17( g) illustrates a sectional view of a master electrodecomprising a mechanical support layer 22, a conducting elastomer layer23, a conducting electrode layer 6 and an insulating pattern layer 5.

FIG. 17( h) illustrates a sectional view of a master electrodecomprising a mechanical support layer 22, a conducting electrode layer6, an insulating pattern layer 5 and intermediate metal layer 24 and aflexible elastomer layer 21.

The master electrode comprises at least one insulating pattern layer andat least one conducting electrode layer (normally inert in the ECPRprocess) and possibly a predeposited anode material in the cavities ofthe master electrode. For instance, the insulting pattern of the masterlayer is a polymer, e.g. a photoresist, an oxide, e.g. SiO₂, a nitride,e.g. SiN, or combinations thereof. The electrolyte comprises suitablesubstances for dissolving and depositing the conducting material inwhich the structures are formed during the ECPR process. For instance,when the conducting material is copper, the electrolyte comprises anaqueous solution of Cu²⁺, SO₄ ²⁻, H⁺ and/or Cl⁻ and additives such aslevelers, accelerators, brighteners, suppressors and wetting agents.Appropriate additives can be poly-ethylene-glycol (PEG), chloride ions,MPSA, SPS and/or sodium-lauryl-sulfate.

FIG. 18 illustrates the schematic eight step process of conventionallithography and electroplating.

FIG. 19 illustrates the schematic three step process of producing aplating pattern with the ECPR method.

In some embodiments, an etching pattern is created with anelectrochemical process by using the conducting electrode layer of themaster electrode as cathode whereby material is dissolved from thesubstrate, transferred in the electrolyte and deposited on the cathodethereby creating ECPR etched structures on the substrate correspondingto the pattern of insulating pattern layer on the master electrode.Since the material that is being dissolved from the substrate, which isanode, also is deposited at the conducting electrode layer, which iscathode, the amount of dissolved anode material in the electrolyteremains close to constant during the electrochemical process. If thedeposition rate of the dissolved material is zero, the concentration ofdissolved anode material ions in the electrolyte increases quickly, thisslows down the electrochemical reaction until it eventually stops. A toohigh ion concentration can also result in precipitation of salts. Inthis case, only small amounts could be dissolved from the substrate andonly thin layers could be patterned. Instead, by making sure that thedissolution reaction has an appropriate deposition reaction, substrateswith thicker layers can be etched. The dissolution and depositionreaction in the electrochemical process is determined by thethermodynamic and kinetic reaction at a given applied potential in aspecific system of anode, cathode and electrolyte. By choosing theappropriate anode material, cathode material and electrolyte, thedesired dissolution and deposition reaction can be achieved since theyare thermodynamically and kinetically favorable in the chosen system.

One example of appropriate anode, cathode and electrolyte system is Nias anode material, Au as a cathode material and a Watt's bath used aselectrolyte. In some aspects, the deposition reaction does not have tobe corresponding to the dissolution reaction exactly. As long as thedeposition rate of the dissolved material is larger than zero, thebuildup of ion concentration of anode material in the electrolyte willbe slow which means that it will take longer time before the reactionstops and hence thicker layers on the substrate can be etched. Forinstance, the deposition rate of the dissolved ions can be 90-100% ofthe dissolution rate. In this example, the ion concentration ofdissolved anode will increase slowly, but in some aspects a desiredetched thickness can be achieved before the concentration becomes toohigh. In some cases, the dissolution rate can be lower than thedeposition speed, which eventually leads to depletion of ionconcentration in the electrolyte. However, if the dissolution reactionis not too low compared to the deposition reaction (e.g. >90% of thedeposition rate), a desired thickness can still be etched from thesubstrate before depletion of anode material ions in the electrolyte.One example of an inappropriate system is Ag as anode material, Al ascathode material and an alkaline silver cyanide bath as an electrolyte.In this example, the deposition rate of silver ions is zero, which willlead to a fast buildup of silver ions in the electrolyte.

A plating pattern is created by an electrochemical process by using theconducting electrode layer of the master electrode as anode and havingpredeposited anode material on the anode inside the cavities defined bythe master electrode whereby said anode material is dissolved,transferred in the electrolyte and deposited on the substrate, beingcathode, thereby creating ECPR plated structures on the substratecorresponding to the cavities of the insulating pattern layer on themaster electrode.

One problem with prior art processes which do not have a predepositedmaterial is that anode material is dissolved directly from conductingelectrode layer 6 in the master 4, the master electrode will eventuallywear out since the dissolved material is undercutting the insulatingpattern layer 5, as illustrated in FIG. 20( a). By having a predepositedanode material 10 in the cavities of the master electrode 4, it ispossible the have a conducting electrode layer 5 comprising an inertmaterial that does not dissolve during the electrochemical process andno undercutting of the insulating pattern layer 5 occurs, as illustratedin FIG. 20(b). Thereby, the master electrode can be reused a largenumber of times, which leads to a more cost and time efficientpatterning process.

Another problem with prior art processes, which do not have predepositedmaterial is that the dissolved material that is undercutting theinsulating pattern layer leads to that the anode area increasesdifferently in large contra small cavities in the insulating patternlayer. In large cavities, the area increase due to undercutting issmaller than in small cavities, as illustrated in FIG. 20( a).Increasing the anode area leads to a higher current density (i.e.plating rate) at the cathode. Hence, the structures plated in the smallcavities of the insulating pattern layer will be deposited with a higherplating rate than the structures in the large cavities leading to anuneven thickness distribution that depends on the pattern. Also thisproblem is solved by having a predeposited material, since no areaincrease will occur and thereby the current density (plating rate) willbe the same in all cavities, non-depending on the size of the patterns.

Also, the dissolution of predeposited material prevents the depletion ofthe concentration of ions in the electrolyte that are deposited on thecathode. A depletion of ions in the electrolyte would gradually slowdown the deposition process until it eventually stops and only thinlayers of plated structures would be achievable. By having a sufficientamount of predeposited material that is being dissolved during theelectrochemical deposition reaction, the ion concentration remainsstable and thicker layers of plated structures can be achieved. Bychoosing the appropriate predeposited material (anode), seed layermaterial (cathode) and electrolyte, the desired dissolution anddeposition reaction can be achieved since they are thermodynamically andkinetically favorable in the chosen system. One example of anappropriate choice of electrochemical system is: having Cu aspredeposited material (anode), Cu as seed layer (cathode) and an acidiccopper sulfate bath as an electrolyte. In some cases, the depositionreaction does not have to be corresponding to the dissolution reactionexactly. As long as the dissolution rate of the predeposited material islarger than zero, the depletion of ion concentration in the electrolytewill be slower which means that it will take longer time before thereaction stops and hence thicker layers can be plated. For instance, thedissolution rate can be 90-100% of the deposition rate. In this example,the ion concentration of material being deposited will decrease slowly,but in some aspects a desired plated thickness can be achieved beforethe concentration becomes too low.

As mentioned above, the method may include applying a barrier/cappingcoating 16 onto the top layer on the substrate 2 prior to applying adielectric material 9. This may be done with a mask-less method, asmentioned in said step “(f)”, selectively coating the ECPR platedstructures 11. In some embodiments, it can be suitable not to remove thebarrier/capping layer 14 after removing the seed layer 1 and prior toapplying the barrier/capping coating 16. In this way, top layer on thesubstrate 2, for instance a dielectric material layer, is protected bythe barrier/capping layer 14 in the following step of applying thebarrier/capping coating 16. The barrier/capping layer 14 can be of amaterial onto which no barrier/capping coating 16 is deposited duringthe mask-less method used for applying the coating onto the ECPR platedstructures 11. After applying the barrier/capping coating selectivelyonto the ECPR plated structures 11, the barrier/capping layer 14 betweenthe structures can be removed using said removing methods for the layerdescribed in said step “(e)”. The barrier/capping material may comprisea material that can be etched with a dry-etch method described in saidstep “(e)”. The barrier/capping coating 16 may comprise a material thatis not affected by the removing method used for the barrier/cappinglayer 14 or at least less affected than the material used for thebarrier/capping layer 14.

In some embodiments, a conducting or semiconducting layer is usedinstead of said dielectric layer. In some cases, a sacrificial layer maybe used instead of said dielectric layer, said sacrificial layer beingremoved after forming said multiple structure layers. In further cases,the same layer may comprise structural material, sacrificial materialand dielectric material.

The height of the different material layers is indicated in the drawingsto be of the same size. However, each individual layer can be of anydimension as required by the construction. However, normally, each layeris of a uniform height over the entire surface of the substrate, i.e.the layer has a substantially constant thickness.

Herein above, several method steps have been described in differentcombinations and constellations. However, it is emphasized that othercombinations may be performed as occur to a skilled person reading thisspecification, and such combinations are within the scope of the presentinvention. Moreover, the different steps can be modified or alteredstill within the scope of the invention. The invention is only limitedby the appended patent claims.

1-76. (canceled)
 77. A method of forming a multilayer structure byelectrochemical plating on a substrate, wherein said substrate or saidsubstrate layer comprises a via, the method comprising: a) arranging anelectrically conducting seed layer on at least a part of the substrateor a substrate layer and said via; b) applying a master electrode, inwhich said insulating pattern layer is provided with cavities at leastopposite to said vias, and wherein said cavities have a width which isslightly smaller, equal or slightly larger than the width of said via;and a predeposited anode material is arranged in said cavities; c)applying a voltage between said conducting electrode layer and said seedlayer for transferring at least some parts of said anode material forforming plated structures in said vias.
 78. A method of forming astructure by electrochemical plating on a substrate provided with aconducting material structure, comprising: a) arranging an electricallyconducting seed layer on at least a part of the substrate; b) applying amaster electrode on said seed layer, said master electrode having anelectrically conducting electrode layer, an anode material and aninsulating pattern layer for forming at least one electrochemical cellcomprising an electrolyte in the area enclosed by said anode material,said insulating pattern layer and said seed layer, said cavity enclosingat least a part of said conducting material structure; wherein saidanode material is being in electrical contact with said conductingelectrode layer; c) applying a voltage between said conducting electrodelayer and said seed layer so that said seed layer forms a cathode fortransferring at least some of said anode material in said at least onecell to said seed layer for forming plated structures onto said seedlayer and said conducting material structures corresponding to thecavities of the insulating pattern layer on the master electrode; d)separating said master electrode from said substrate.
 79. The method ofclaim 78, further comprising: b1) applying a further master electrode onsaid seed layer, said master electrode having an electrically conductingelectrode layer, an anode material and an insulating pattern layer forforming at least one electrochemical cell comprising an electrolyte inthe area enclosed by said anode material, said insulating pattern layerand said seed layer, said cavity enclosing at least a part of saidconducting material structure and plated structures; wherein said anodematerial is being in electrical contact with said conducting electrodelayer; c1) applying a voltage between said conducting electrode layerand said seed layer so that said seed layer forms a cathode fortransferring at least some of said anode material in said at least onecell to said seed layer for forming plated structures onto said seedlayer and said conducting material structures and plated structurescorresponding to the cavities of the insulating pattern layer on themaster electrode; and d1) separating said master electrode from saidsubstrate.
 80. The method of any one of claims 77 and 78, furthercomprising: e) removing said seed layer in non-plated areas.
 81. Themethod of any one of claims 77 and 78, wherein said planarization stepcomprises performing a polishing step until said material surface issubstantially planar and a subsequent etching step of said materialsurface until at least part of said structures is uncovered.
 82. Themethod of any one of claims 77 and 78, wherein a planarizing material isapplied into said material layer prior to performing said planarizationstep of said material layer.
 83. The method of claim 82, wherein saidplanarizing material is applied with a method selected from the groupcomprising: spin-coating, spray-coating, powder-coating, dip-coating,roller-coating, sputtering, PVD, CVD, PECVD, electrodeposition, andcombinations thereof.
 84. The method of any one of claims 77 and 78,wherein an end-point detection method is used so as to determine whensaid planarization step is completed.
 85. The method of any one ofclaims 77 and 78, wherein the step of planarization comprises: applyinga plate above said material layer and applying a pressure on said platefor equalizing the material in said material layer, while in a flowablecondition.
 86. The method of claim 85, wherein said flowable conditionis obtained by heating said material layer, whereupon the material iscooled after planarization.
 86. The method of claim 85, wherein saidstep of applying the plate is performed before curing said material,whereupon the material is cured after planarization, such as by applyinginfrared or ultraviolet radiation.
 87. The method of any one of claims77 and 78, wherein the seed layer is made of a material selected fromthe group comprising: Ru, Os, Hf, Re, Cr, Au, Ag, Cu, Sn, Ti, TiN, TiW,Ni, NiB, NiP, NiCo NiBW, NiM-P, Al, Pd, Pt, W, Ta, TaN, Rh, Wo, Co,CoReP, CoP, CoWP, CoWB, CoWBP alloys of these material, Si, conductingpolymers such as polyaniline; solder materials, such as SnPb, SnAg,SnAgCu, SnCu; alloys, such as monel and permalloy; and alloys thereofand combinations thereof.
 88. The method of claim 87, wherein the seedlayer is applied by a method selected from the group comprising:chemical-vapor-deposition (CVD), metallorganic-chemical-vapor-deposition(MOCVD), physical-vapor-deposition (PVD), atomic layer deposition (ALD),sputtering, electroless plating, electroplating, electrografting,immersion deposition, and combinations thereof.
 89. The method of anyone of claims 77 and 78, further comprising applying a barrier/cappinglayer before step a) or f).
 90. The method of claim 89, wherein saidbarrier/capping material comprises at least one layer of material thatprevents corrosion, diffusion or electromigration of layers which areinterfacing with said barrier/capping material.
 91. The method of claim89, wherein said barrier/capping material is applied by a methodselected from the group comprising: electrodeposition, MOCVD, CVD, PVD,ALD, sputtering, electroless deposition, immersion deposition,electrografting and combinations thereof.
 92. The method of claim 91,wherein said barrier/capping material is applied with a mask-lessselective deposition method, such as electroless deposition, whereindeposition is obtained only in surfaces active to said depositionprocess, such as on said structure layer and not on said arrangedmaterial layer.
 93. The method of any one of claims 77 and 78, whereinsaid barrier/capping material is used as a seed layer in said step a).94. The method of any one of claims 77 and 78, further comprisingapplying an adhesion layer before applying said seed layer and/or beforeapplying said barrier/capping material; wherein said adhesion layerincrease the adhesion of said seed layer or barrier/capping layer tosaid arranged material layer or structures.
 95. The method of any one ofclaims 77 and 78, wherein said forming of at least one electrochemicalcell comprises a method for aligning said insulating pattern layer to apatterned layer on said substrate, wherein said aligning methodcomprises using alignment marks on the front side and/or back side ofsaid master electrode which are aligned to corresponding alignment markson said substrate.
 96. The method of any one of claims 77 and 78,wherein said formed electrochemical cell comprises a solution ofcations, such as copper or nickel ions, and anions, such as sulfateions, for electrochemical etching and/or plating.
 97. The method ofclaim 96, wherein said electrolyte comprises suppressors, levelersand/or accelerators, for instance PEG (poly-ethylene glycol) togetherwith chloride ions and/or with SPS (bis-(3-sulfopropyl)-disulfide), MPSAand/or sodium-lauryl-sulphate.
 98. The method of any one of claims 77and 78, wherein said anode material is arranged onto said conductingelectrode layer in the cavities of said insulating pattern layer using amethod selected from the group comprising: electroplating, electrolessplating, immersion plating, CVD, MOCVD, powder-coating, chemicalgrafting, electrografting and combinations thereof.
 99. The method ofany one of claims 77 and 78, wherein said separation step d) isperformed by holding said substrate in a fixed position and moving saidmaster electrode in a direction perpendicular to the substrate surface;or by holding said master electrode in a fixed position and moving saidsubstrate in a direction perpendicular to the master electrode surface;or by performing the separation in a less parallel manner so as to easethe separation; or by a combination thereof.
 100. The method of any oneof claims 77 and 78, wherein said step e) removing said seed layer isperformed by wet-etching, dry-etching, electrochemical etching or bycombinations thereof.
 101. The method of claim 100, further comprisingapplying a protective coating which is covering all or substantially allof said seed layer, barrier/capping layer and/or structure layer;treating said protective coating with an anisotropic etch, therebyuncovering the top of said seed layer, barrier/capping layer and/orstructure layer between the structures while leaving a protective layeron the side walls of said structures; removing said seed layer and/orbarrier layer between said structures.
 102. The method of any one ofclaims 77 and 78, wherein said material layer is at least one layer of adielectric material and is applied by a method selected from the groupcomprising: spin-coating, spray-coating, powder-coating, dip-coating,roller-coating, sputtering, PVD, CVD,Plasma-Enhanced-Chemical-Vapor-Deposition (PECVD), electrodeposition,and combinations thereof.
 103. The method of any one of claims 77 and78, wherein said material layer is at least one layer of a metal and isapplied by a method selected from the group comprising:electrodeposition, MOCVD, CVD, PVD, ALD, sputtering, electrolessdeposition, immersion deposition, electrografting and combinationsthereof.
 104. The method of any one of claims 77 and 78, furthercomprising: arranging an etch-stop layer on top of the structures beforethe step f) of arranging the material.
 105. The method of any one ofclaims 77 and 78, wherein said material layer is a porous low-kdielectric material and a pore sealing operation is performed prior toapplying further layers of material onto it.
 106. The method of any oneof claims 77 and 78, further comprising forming a structure layer beforestep h); wherein forming a structure layer comprises lithographymethods; deposition methods such as electrodeposition, electrolessdeposition; wet-etching or dry-etching methods.